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| author | Chad Rosier <mcrosier@apple.com> | 2011-06-14 22:29:10 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2011-06-14 22:29:10 +0000 |
| commit | 818e1167234feae4b1ccb331b9dd4121b303eeec (patch) | |
| tree | 56c5401648145bdef155b756ced4cf8eb5c7ff7b /llvm/lib/CodeGen | |
| parent | 1bf96ac60717facfbaf38070798e3805e955f6d4 (diff) | |
| download | bcm5719-llvm-818e1167234feae4b1ccb331b9dd4121b303eeec.tar.gz bcm5719-llvm-818e1167234feae4b1ccb331b9dd4121b303eeec.zip | |
When pattern matching during instruction selection make sure shl x,1 is not
converted to add x,x if x is a undef. add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.
llvm-svn: 133022
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 6f940760e03..3cf7a2be6f3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3030,6 +3030,9 @@ SDValue DAGCombiner::visitSHL(SDNode *N) { // fold (shl x, 0) -> x if (N1C && N1C->isNullValue()) return N0; + // fold (shl undef, x) -> 0 + if (N0.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); // if (shl x, c) is known to be zero, return 0 if (DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnesValue(OpSizeInBits))) |
