| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Revert "Reapply "DebugInfo: Ensure that all debug location scope chains from ... | Eric Christopher | 2014-07-18 | 2 | -8/+4 |
| * | DebugInfo: Assert that all abstract scopes are subprograms, rather than condi... | David Blaikie | 2014-07-18 | 1 | -2/+1 |
| * | Reapply "DebugInfo: Ensure that all debug location scope chains from instruct... | David Blaikie | 2014-07-18 | 2 | -4/+8 |
| * | ARM: support legalisation of "fptrunc ... to half" operations. | Tim Northover | 2014-07-18 | 2 | -0/+24 |
| * | CodeGen: soften f16 type by default instead of marking legal. | Tim Northover | 2014-07-18 | 1 | -0/+7 |
| * | AArch64: Constant fold converting vector setcc results to float. | Jim Grosbach | 2014-07-18 | 1 | -0/+26 |
| * | Revert "[x86] Fold extract_vector_elt of a load into the Load's address compu... | Michael J. Spencer | 2014-07-18 | 1 | -124/+90 |
| * | CodeGen: generate single libcall for fptrunc -> f16 operations. | Tim Northover | 2014-07-17 | 4 | -19/+29 |
| * | CodeGen: extend f16 conversions to permit types > float. | Tim Northover | 2014-07-17 | 6 | -21/+48 |
| * | Fixed formatting, removed bug reference, renamed testcase | Sanjay Patel | 2014-07-16 | 1 | -3/+4 |
| * | [FastISel] Local values shouldn't be alive across an inline asm call with sid... | Juergen Ributzka | 2014-07-16 | 1 | -0/+5 |
| * | trivial fix for PR20314 | Sanjay Patel | 2014-07-16 | 1 | -1/+4 |
| * | [RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the Targ... | Chris Bieneman | 2014-07-16 | 1 | -2/+1 |
| * | CodeGen: don't form illegail EXTLOAD operations. | Tim Northover | 2014-07-16 | 1 | -4/+2 |
| * | Remove TLI from isInTailCallPosition's arguments. NFC. | Juergen Ributzka | 2014-07-16 | 3 | -5/+5 |
| * | Move Post RA Scheduling flag bit into SchedMachineModel | Sanjay Patel | 2014-07-15 | 1 | -3/+20 |
| * | [RegisterCoalescer] Add new subtarget hook allowing targets to opt-out of coa... | Chris Bieneman | 2014-07-15 | 1 | -0/+17 |
| * | [DAGCombiner] Add more rules to fold shuffles. | Andrea Di Biagio | 2014-07-15 | 1 | -7/+17 |
| * | [FastISel] Insert patchpoint instruction before the target generated call ins... | Juergen Ributzka | 2014-07-15 | 1 | -1/+2 |
| * | [FastISel] Fix patchpoint lowering to set the result register. | Juergen Ributzka | 2014-07-15 | 1 | -5/+6 |
| * | [DAGCombiner] Avoid calling method 'isShuffleMaskLegal' on illegal vector types. | Andrea Di Biagio | 2014-07-15 | 1 | -0/+2 |
| * | CodeGen: Stick constant pool entries in COMDAT sections for WinCOFF | David Majnemer | 2014-07-14 | 2 | -10/+26 |
| * | [DAGCombiner] Add more rules to combine shuffle vector dag nodes. | Andrea Di Biagio | 2014-07-14 | 1 | -0/+44 |
| * | CodeGen: Add a getSectionKind method to MachineConstantPoolEntry | David Majnemer | 2014-07-14 | 2 | -15/+32 |
| * | Unify the lowering of arguments during SjLj prepare. | Bill Wendling | 2014-07-14 | 1 | -28/+10 |
| * | fixed typo | Sanjay Patel | 2014-07-14 | 1 | -1/+1 |
| * | CodeGen: add missing include | Saleem Abdulrasool | 2014-07-14 | 1 | -0/+1 |
| * | Support lowering of empty aggregates. | Bill Wendling | 2014-07-14 | 1 | -11/+11 |
| * | [DAGCombiner] Fix a crash caused by a missing check for legal type when tryin... | Andrea Di Biagio | 2014-07-13 | 1 | -1/+1 |
| * | Templatify DominanceFrontier. | Matt Arsenault | 2014-07-12 | 2 | -0/+55 |
| * | Avoid a warning from MSVC on "*/" in this code by inserting a space | Reid Kleckner | 2014-07-12 | 1 | -1/+1 |
| * | [FastISel] Add target-independent patchpoint intrinsic support. WIP. | Juergen Ributzka | 2014-07-11 | 1 | -0/+169 |
| * | [FastISel] Add basic infrastructure to support a target-independent call lowe... | Juergen Ributzka | 2014-07-11 | 1 | -2/+208 |
| * | [FastISel] Make isInTailCallPosition independent of SelectionDAG. | Juergen Ributzka | 2014-07-11 | 2 | -6/+5 |
| * | [FastISel] Breakout intrinsic lowering into a separate function and add a tar... | Juergen Ributzka | 2014-07-11 | 1 | -34/+39 |
| * | ARM: Allow __fp16 as a function arg or return type for AArch64 | Oliver Stannard | 2014-07-11 | 1 | -1/+1 |
| * | Revert "Reapply "DebugInfo: Ensure that all debug location scope chains from ... | David Blaikie | 2014-07-11 | 2 | -8/+4 |
| * | Reapply "DebugInfo: Ensure that all debug location scope chains from instruct... | David Blaikie | 2014-07-10 | 2 | -4/+8 |
| * | SelectionDAG: Factor FP_TO_SINT lower code out of DAGLegalizer | Jan Vesely | 2014-07-10 | 2 | -58/+65 |
| * | Revert "Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (t... | Matt Arsenault | 2014-07-10 | 1 | -0/+13 |
| * | [DAG] Further improve the logic in DAGCombiner that folds a pair of shuffles ... | Andrea Di Biagio | 2014-07-10 | 1 | -14/+51 |
| * | [x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogous | Chandler Carruth | 2014-07-10 | 6 | -9/+113 |
| * | Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) ... | NAKAMURA Takumi | 2014-07-10 | 1 | -14/+0 |
| * | Make it possible for ints/floats to return different values from getBooleanCo... | Daniel Sanders | 2014-07-10 | 10 | -50/+95 |
| * | [AArch64]Fix an assertion failure in DAG Combiner about concating 2 build_vec... | Hao Liu | 2014-07-10 | 1 | -4/+18 |
| * | [SDAG] Make the new zext-vector-inreg node default to expand so targets | Chandler Carruth | 2014-07-09 | 1 | -1/+4 |
| * | Recommit r212203: Don't try to construct debug LexicalScopes hierarchy for fu... | David Blaikie | 2014-07-09 | 4 | -4/+33 |
| * | Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine. | Matt Arsenault | 2014-07-09 | 1 | -0/+14 |
| * | [x86] Fix a bug in my new zext-vector-inreg DAG trickery where we were | Chandler Carruth | 2014-07-09 | 2 | -0/+36 |
| * | Sink two variables only used in an assert into the assert itself. Should | Chandler Carruth | 2014-07-09 | 1 | -3/+3 |
