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* Fix for PR4051. When 2address pass delete an instruction, update kill info ↵Evan Cheng2009-04-281-8/+79
| | | | | | when necessary. llvm-svn: 70279
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-2812-87/+85
| | | | llvm-svn: 70275
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-2812-84/+87
| | | | | | | | | | | use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... llvm-svn: 70270
* Fix PR4076. Correctly create live interval of physical register with ↵Evan Cheng2009-04-271-10/+20
| | | | | | two-address update. llvm-svn: 70245
* Don't skip the CopyMI when removing kill markers.Owen Anderson2009-04-271-2/+0
| | | | | | | This should have no effect on generated code, but makes the intermediate state of the coalescer more sane. llvm-svn: 70238
* Now that PR2957 is resolved, remove a bunch ofDuncan Sands2009-04-274-90/+4
| | | | | | no-longer needed workarounds. llvm-svn: 70234
* 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.Nate Begeman2009-04-275-449/+363
| | | | | | | | | | | | | | PR2957 ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. llvm-svn: 70225
* Fix PR4056. It's possible a physical register def is dead if its implicit ↵Evan Cheng2009-04-271-2/+2
| | | | | | use is deleted by two-address pass. llvm-svn: 70213
* Also delete last unused val#.Evan Cheng2009-04-271-0/+6
| | | | llvm-svn: 70212
* When transforming sext(trunc(load(x))) into sext(smaller load(x)),Dan Gohman2009-04-271-1/+1
| | | | | | | the trunc is directly replaced with the smaller load, so don't try to create a new sext node. This fixes PR4050. llvm-svn: 70179
* Reuse unused val#'s to avoid running out of memory in extreme cases.Evan Cheng2009-04-251-1/+5
| | | | llvm-svn: 70069
* Refactor the code to grab the low and high parts of a valueDan Gohman2009-04-254-126/+38
| | | | | | using EXTRACT_ELEMENT into a utility function. llvm-svn: 70056
* Add a top-level comment about DAGCombiner's role in the compiler.Dan Gohman2009-04-251-0/+4
| | | | llvm-svn: 70052
* Do not share a single unknown val# for all the live ranges merged into a ↵Evan Cheng2009-04-251-19/+13
| | | | | | physical sub-register live interval. When coalescer is merging in clobbered virtaul register live interval into a physical register live interval, give each virtual register val# a separate val# in the physical register live interval. Otherwise, the coalescer would have lost track of the definitions information it needs to make correct coalescing decisions. llvm-svn: 70026
* Fix PR 4057, a crash doing float->char const folding.Dale Johannesen2009-04-241-3/+4
| | | | | | | | This particular one is undefined behavior (although this isn't related to the crash), so it will no longer do it at compile time, which seems better. llvm-svn: 69990
* Revert 69952. Causes testsuite failures on linux x86-64.Rafael Espindola2009-04-245-353/+447
| | | | llvm-svn: 69967
* PR2957Nate Begeman2009-04-245-447/+353
| | | | | | | | | | | | | | ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next. llvm-svn: 69952
* Instead of requiring TLI.LowerCallTo to return an ISD::BUILD_PAIR,Dan Gohman2009-04-241-60/+118
| | | | | | | | use ISD::EXTRACT_ELEMENT. SelectionDAG has a special fast-path for the cast of an EXTRACT_ELEMENT with a BUILD_PAIR operand, for the common case. llvm-svn: 69948
* Factor out a bit of code that appears in several places into aDan Gohman2009-04-233-14/+16
| | | | | | utility function. llvm-svn: 69937
* Handle Void types in ComputeValueVTs. This doesn't currently occur,Dan Gohman2009-04-231-0/+3
| | | | | | | but this change makes the code more general and easier to adapt for new purposes. llvm-svn: 69935
* Update comments.Evan Cheng2009-04-231-2/+2
| | | | llvm-svn: 69919
* Fix an obvious type.Evan Cheng2009-04-231-1/+1
| | | | llvm-svn: 69918
* It has finally happened. Spiller is now using live interval info.Evan Cheng2009-04-215-40/+68
| | | | | | This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue. llvm-svn: 69743
* Fix Visual Studio 2008 build failure.Devang Patel2009-04-211-3/+3
| | | | | | Patch by Marius Wachtler llvm-svn: 69637
* Make X86's copyRegToReg able to handle copies to and from subclasses.Dan Gohman2009-04-201-25/+0
| | | | | | | This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp unnecessary. Derived from a patch by Jakob Stoklund Olesen. llvm-svn: 69635
* Simplify this code. getConstant knows how to makeDan Gohman2009-04-201-10/+3
| | | | | | broadcasted vector constants. llvm-svn: 69634
* Move duplicated AddLiveIn function from X86 and ARM backends to be a methodBob Wilson2009-04-201-0/+10
| | | | | | | in the MachineFunction class, renaming it to addLiveIn for consistency with the same method in MachineBasicBlock. Thanks for Anton for suggesting this. llvm-svn: 69615
* Revise my previous change 68996 as suggested by Duncan.Bob Wilson2009-04-203-9/+5
| | | | llvm-svn: 69607
* - Remove an arbitrary spill weight tweak that should not have been there.Evan Cheng2009-04-201-5/+26
| | | | | | - Find more reloads from SS. llvm-svn: 69606
* Added a linearscan register allocation optimization. When the register ↵Evan Cheng2009-04-202-67/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g. %reg1498<def> = MOV32rm %reg1024, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0] %reg1506<def> = MOV32rm %reg1024, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0] %reg1486<def> = MOV32rr %reg1506 %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead> %reg1510<def> = MOV32rm %reg1024, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0] => %reg1498<def> = MOV32rm %reg2036, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0] %reg1506<def> = MOV32rm %reg2037, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0] %reg1486<def> = MOV32rr %reg1506 %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead> %reg1510<def> = MOV32rm %reg2038, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0] From linearscan's point of view, each of reg2036, 2037, and 2038 are separate registers, each is "killed" after a single use. The reloaded register is available and it's often clobbered right away. e.g. In thise case reg1498 is allocated EAX while reg2036 is allocated RAX. This means we end up with multiple reloads from the same stack slot in the same basic block. Now linearscan recognize there are other reloads from same SS in the same BB. So it'll "downgrade" RAX (and its aliases) after reg2036 is allocated until the next reload (reg2037) is done. This greatly increase the likihood reloads from SS are reused. This speeds up sha1 from OpenSSL by 5.8%. It is also an across the board win for SPEC2000 and 2006. llvm-svn: 69585
* Now that BUILD_VECTOR operands are allowed to beDuncan Sands2009-04-191-9/+6
| | | | | | | | bigger than the vector element type, turn checking of the operand type back on again, appropriately adjusted. llvm-svn: 69516
* Fix PR3898, which manifests as failures on are an Xcore,Chris Lattner2009-04-181-1/+1
| | | | | | patch by Jakob Stoklund Olesen! llvm-svn: 69472
* Don't try to make BUILD_VECTOR operands have the sameDuncan Sands2009-04-186-63/+35
| | | | | | | | | | | | | | | | | type as the vector element type: allow them to be of a wider integer type than the element type all the way through the system, and not just as far as LegalizeDAG. This should be safe because it used to be this way (the old type legalizer would produce such nodes), so backends should be able to handle it. In fact only targets which have legal vector types with an illegal promoted element type will ever see this (eg: <4 x i16> on ppc). This fixes a regression with the new type legalizer (vec_splat.ll). Also, treat SCALAR_TO_VECTOR the same as BUILD_VECTOR. After all, it is just a special case of BUILD_VECTOR. llvm-svn: 69467
* Add a new LiveInterval::overlaps(). It checks if the live interval overlaps ↵Evan Cheng2009-04-181-0/+16
| | | | | | a range specified by [Start, End). llvm-svn: 69434
* Inline asm's were still introducing bogus dependencies;Dale Johannesen2009-04-181-1/+7
| | | | | | my earlier patch to this code only fixed half of it. llvm-svn: 69408
* Teach spiller to unfold instructions which modref spill slot when a scratchEvan Cheng2009-04-172-11/+227
| | | | | | | | | | | | | | | | | | | | register is available and when it's profitable. e.g. xorq %r12<kill>, %r13 addq %rax, -184(%rbp) addq %r13, -184(%rbp) ==> xorq %r12<kill>, %r13 movq -184(%rbp), %r12 addq %rax, %r12 addq %r13, %r12 movq %r12, -184(%rbp) Two more instructions, but fewer memory accesses. It can also open up opportunities for more optimizations. llvm-svn: 69341
* In the list-burr's pseudo two-addr dependency heuristics, don'tDan Gohman2009-04-161-0/+10
| | | | | | | | | add dependencies on nodes with exactly one successor which is a COPY_TO_REGCLASS node. In the case that the copy is coalesced away, the dependence should be on the user of the copy, rather than the copy itself. llvm-svn: 69309
* Handle SUBREG_TO_REG instructions with the same heuristicsDan Gohman2009-04-161-5/+7
| | | | | | as INSERT_SUBREG instructions in the list-burr scheduler. llvm-svn: 69308
* Do not treat beginning of inlined scope as beginning of normal function ↵Devang Patel2009-04-162-2/+20
| | | | | | | | | | | | | | | | | | | | | scope if the location info is missing. Insetad of doing ... if (inlined_subroutine && known_location) DW_TAG_inline_subroutine else DW_TAG_subprogram do if (inlined_subroutine) { if (known_location) DW_TAG_inline_subroutine } else { DW_TAG_subprogram } llvm-svn: 69300
* Record line number at the beginning of a func.start.Devang Patel2009-04-162-2/+2
| | | | | | This line was accidently lost yesterday. llvm-svn: 69286
* In -fast mode do what FastISel does.Devang Patel2009-04-162-30/+71
| | | | | | This code could use some refactoring help! llvm-svn: 69254
* If FastISel is run and it has known DebugLoc then use it.Devang Patel2009-04-162-3/+7
| | | | llvm-svn: 69253
* If location where the function was inlined is not know then do not emit ↵Devang Patel2009-04-161-5/+11
| | | | | | debug info describing inlinied region. llvm-svn: 69252
* s/RootDbgScope/FunctionDbgScope/gDevang Patel2009-04-151-13/+13
| | | | llvm-svn: 69216
* Add DISubprogram is not null check.Devang Patel2009-04-151-2/+4
| | | | | | This fixes test/CodeGen//2009-01-21-invalid-debug-info.m test case. llvm-svn: 69210
* Generalize one of the SelectionDAG::ReplaceAllUsesWith overloadsDan Gohman2009-04-152-9/+10
| | | | | | | | to support replacing a node with another that has a superset of the result types. Use this instead of calling ReplaceAllUsesOfValueWith for each value. llvm-svn: 69209
* Check isInlinedSubroutine() before creating DW_TAG_inlined_subroutine.Devang Patel2009-04-151-1/+2
| | | | llvm-svn: 69202
* Fix MachineInstr::getNumExplicitOperands to countDan Gohman2009-04-151-2/+2
| | | | | | variadic operands correctly. Patch by Jakob Stoklund Olesen! llvm-svn: 69190
* Move MachineRegisterInfo::setRegClass out of line.Dan Gohman2009-04-151-0/+20
| | | | llvm-svn: 69126
* Move MachineJumpTableInfo::ReplaceMBBInJumpTables out of line.Dan Gohman2009-04-151-0/+17
| | | | llvm-svn: 69125
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