summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Start using SplitKit and MachineLoopRanges in RegAllocGreedy in preparation ofJakob Stoklund Olesen2010-12-152-11/+39
| | | | | | | | live range splitting around loops guided by register pressure. So far, trySplit() simply prints a lot of debug output. llvm-svn: 121918
* Add MachineLoopRanges analysis.Jakob Stoklund Olesen2010-12-152-0/+86
| | | | | | | | A MachineLoopRange contains the intervals of slot indexes covered by the blocks in a loop. This representation of the loop blocks is more efficient to compare against interfering registers during register coalescing. llvm-svn: 121917
* Teach machine cse to commute instructions.Evan Cheng2010-12-151-2/+19
| | | | llvm-svn: 121903
* Move Value::getUnderlyingObject to be a standaloneDan Gohman2010-12-151-2/+3
| | | | | | | function so that it can live in Analysis instead of VMCore. llvm-svn: 121885
* Fix build.Jakob Stoklund Olesen2010-12-151-1/+1
| | | | llvm-svn: 121872
* Detect and enumerate bypass loops.Jakob Stoklund Olesen2010-12-152-0/+39
| | | | | | | | Bypass loops have the current live range live through, but contain no uses or defs. Splitting around a bypass loop can free registers for other uses inside the loop by spilling the split range. llvm-svn: 121871
* Separate SplitAnalysis::getSplitLoops().Jakob Stoklund Olesen2010-12-152-7/+14
| | | | | | | This method returns the set of loops with uses that are candidates for splitting. llvm-svn: 121870
* take care of some todos, transforming [us]mul_lohi into Chris Lattner2010-12-151-2/+46
| | | | | | a wider mul if the wider mul is legal. llvm-svn: 121848
* when transforming a MULHS into a wider MUL, there is no need to SRA theChris Lattner2010-12-151-1/+1
| | | | | | result, the top bits are truncated off anyway, just use SRL. llvm-svn: 121846
* Simplify RegAllocGreedy's use of register aliases.Jakob Stoklund Olesen2010-12-141-17/+4
| | | | llvm-svn: 121807
* Simplify CCState's use of register aliases.Jakob Stoklund Olesen2010-12-141-5/+3
| | | | llvm-svn: 121806
* Simplify AggressiveAntiDepBreaker's use of register aliases.Jakob Stoklund Olesen2010-12-141-31/+14
| | | | llvm-svn: 121805
* Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.Jakob Stoklund Olesen2010-12-141-14/+4
| | | | llvm-svn: 121801
* Fix a minor bug in two-address pass. It was missing a commute opportunity.Evan Cheng2010-12-141-1/+2
| | | | | | | | | | | | | | | | | | | regB = move RCX regA = op regB, regC RAX = move regA where both regB and regC are killed. If regB is constrainted to non-compatible physical registers but regC is not constrainted at all, then it's better to commute the instruction. movl %edi, %eax shlq $32, %rcx leaq (%rcx,%rax), %rax => movl %edi, %eax shlq $32, %rcx orq %rcx, %rax rdar://8762995 llvm-svn: 121793
* Move debugging code entirely within DEBUG(). Silences an unused variableMatt Beaumont-Gay2010-12-141-8/+8
| | | | | | warning in the opt build. llvm-svn: 121791
* Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew.Jakob Stoklund Olesen2010-12-143-5/+52
| | | | llvm-svn: 121783
* Use TRI::printReg instead of AbstractRegisterDescription when printingJakob Stoklund Olesen2010-12-143-34/+13
| | | | | | LiveIntervalUnions. llvm-svn: 121781
* Q.seenAllInterferences() must be called after Q.collectInterferingVRegs().Jakob Stoklund Olesen2010-12-141-2/+4
| | | | llvm-svn: 121774
* Remove unused vector.Jakob Stoklund Olesen2010-12-141-1/+1
| | | | llvm-svn: 121741
* Try reassigning all virtual register interferences, not just those with lowerJakob Stoklund Olesen2010-12-141-49/+71
| | | | | | | | spill weight. Filter out fixed registers instead. Add support for reassigning an interference that was assigned to an alias. llvm-svn: 121737
* Add stub for RAGreedy::trySplit.Jakob Stoklund Olesen2010-12-141-0/+16
| | | | llvm-svn: 121736
* Add a couple dag combines to transform mulhi/mullo into a wider multiplyChris Lattner2010-12-131-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. llvm-svn: 121696
* remove the verbose-asm "constant pool double" comments that we were printingChris Lattner2010-12-131-8/+0
| | | | | | | | | | | for each constant pool entry. Using WriteTypeSymbolic here takes time proportional to the size of the module, for each constant pool entry. This speeds up -verbose-asm llc on 252.eon (a random testcase at my disposal) from 4.4s to 2.137s. llc takes 2.11s with asm-verbose off, so this is now a pretty reasonable cost for verbose comments. llvm-svn: 121691
* reduce indentation by using continue, no functionality change.Chris Lattner2010-12-131-38/+41
| | | | llvm-svn: 121662
* Catch attempts to remove a deleted node from the CSE maps. Better toDuncan Sands2010-12-121-3/+2
| | | | | | | catch this here rather than later after accessing uninitialized memory etc. Fires when compiling the testcase in PR8237. llvm-svn: 121635
* Add named timer groups for the different stages of register allocation.Jakob Stoklund Olesen2010-12-113-9/+23
| | | | llvm-svn: 121604
* Move MRI into RegAllocBase. Clean up debug output a bit.Jakob Stoklund Olesen2010-12-103-31/+12
| | | | llvm-svn: 121599
* Remove extraneous close parenthesis.Nick Lewycky2010-12-101-1/+1
| | | | | | Fix build breakage. llvm-svn: 121596
* Move variable that's unused in an NDEBUG build inside the DEBUG() macro, fixingNick Lewycky2010-12-101-3/+4
| | | | | | lib/CodeGen/RegAllocGreedy.cpp:233: error: unused variable 'TRC' [-Wunused-variable] llvm-svn: 121594
* Force the greedy register allocator to always use the inline spiller.Jakob Stoklund Olesen2010-12-103-7/+8
| | | | | | | Soon, RegAllocGreedy will start splitting live ranges, and then deferred spilling won't work anyway. llvm-svn: 121591
* Rip out live range splitting support from the inline spiller.Jakob Stoklund Olesen2010-12-101-56/+1
| | | | | | | | The spiller should only spill. The register allocator will drive live range splitting, it has the needed information about register pressure and interferences. llvm-svn: 121590
* Use AllocationOrder in RegAllocGreedy, fix a bug in the hint calculation.Jakob Stoklund Olesen2010-12-102-25/+10
| | | | llvm-svn: 121584
* Fix miscompilation caused by trivial logic error in the reassignVReg()Jakob Stoklund Olesen2010-12-101-10/+16
| | | | | | interference check. llvm-svn: 121519
* Add an AllocationOrder class that can iterate over the allocatable physicalJakob Stoklund Olesen2010-12-104-1/+127
| | | | | | | | | | | registers for a given virtual register. Reserved registers are filtered from the allocation order, and any valid hint is returned as the first suggestion. For target dependent hints, a number of arcane target hooks are invoked. llvm-svn: 121497
* Fixed version of 121434 with no new memory leaks.Rafael Espindola2010-12-104-27/+16
| | | | llvm-svn: 121471
* Revert my previous patch to make the valgrind bots happy.Rafael Espindola2010-12-104-16/+27
| | | | llvm-svn: 121461
* Initial support for the cfi directives. This is just enough to getRafael Espindola2010-12-094-27/+16
| | | | | | | | | | | f: .cfi_startproc nop .cfi_endproc assembled (on ELF). llvm-svn: 121434
* Initial support for nested CALLSEQ_START/CALLSEQ_END constructs in LegalizeDAG.Stuart Hastings2010-12-091-8/+24
| | | | | | Necessary for byval support on ARM. Radar 7662569. llvm-svn: 121412
* Remember to filter out reserved rergisters from the allocation order.Jakob Stoklund Olesen2010-12-091-1/+1
| | | | llvm-svn: 121411
* Add a forgotten initializer for CheckedFirstInterference.Jakob Stoklund Olesen2010-12-092-2/+5
| | | | llvm-svn: 121410
* Added register reassignment prototype to RAGreedy. It's a simpleAndrew Trick2010-12-095-19/+116
| | | | | | | heuristic to reshuffle register assignments when we can't find an available reg. llvm-svn: 121388
* 80-col fixups.Eric Christopher2010-12-091-9/+15
| | | | llvm-svn: 121356
* IntervalMap iterators are heavyweight, so avoid copying them around and useJakob Stoklund Olesen2010-12-092-5/+25
| | | | | | | | | | | references instead. Similarly, IntervalMap::begin() is almost as expensive as find(), so use find(x) instead of begin().advanceTo(x); This makes RegAllocBasic run another 5% faster. llvm-svn: 121344
* DW_FORM_data1 may not provide sufficient room for vtable index, use _udata ↵Devang Patel2010-12-091-1/+1
| | | | | | | | instead. This fixes radar 8730409. llvm-svn: 121323
* Properly deal with empty intervals when checking for interference.Jakob Stoklund Olesen2010-12-082-1/+3
| | | | llvm-svn: 121319
* Implement very primitive hinting support in RegAllocGreedy.Jakob Stoklund Olesen2010-12-081-1/+25
| | | | | | | The hint is simply tried first and then forgotten if it couldn't be allocated immediately. llvm-svn: 121306
* Store (priority,regnum) pairs in the priority queue instead of providing anJakob Stoklund Olesen2010-12-083-57/+25
| | | | | | | | | | | | | | | | | | | | | | | abstract priority queue interface in subclasses that want to override the priority calculations. Subclasses must provide a getPriority() implementation instead. This approach requires less code as long as priorities are expressable as simple floats, and it avoids the dangers of defining potentially expensive priority comparison functions. It also should speed up priority_queue operations since they no longer have to chase pointers when comparing registers. This is not measurable, though. Preferably, we shouldn't use floats to guide code generation. The use of floats here is derived from the use of floats for spill weights. Spill weights have a dynamic range that doesn't lend itself easily to a fixpoint implementation. When someone invents a stable spill weight representation, it can be reused for allocation priorities. llvm-svn: 121294
* Reword comment slightly.Eric Christopher2010-12-081-1/+1
| | | | llvm-svn: 121293
* Fix comment.Eric Christopher2010-12-081-1/+1
| | | | llvm-svn: 121285
* Trim includes.Jakob Stoklund Olesen2010-12-081-4/+0
| | | | llvm-svn: 121283
OpenPOWER on IntegriCloud