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| author | Nick Lewycky <nicholas@mxc.ca> | 2010-12-10 23:14:35 +0000 |
|---|---|---|
| committer | Nick Lewycky <nicholas@mxc.ca> | 2010-12-10 23:14:35 +0000 |
| commit | bb8610635f384f51969376238c53595761d814bf (patch) | |
| tree | c792bb964081d004622fc31fc5d59ae31d8e2f27 /llvm/lib/CodeGen | |
| parent | 546b691c734e62c7ee9a9f7d2425dac855bda9d3 (diff) | |
| download | bcm5719-llvm-bb8610635f384f51969376238c53595761d814bf.tar.gz bcm5719-llvm-bb8610635f384f51969376238c53595761d814bf.zip | |
Remove extraneous close parenthesis.
Fix build breakage.
llvm-svn: 121596
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocGreedy.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index e88016fbb37..af2c55e7d89 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -232,7 +232,7 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, // Check for an available register in this class. DEBUG({ const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg); - dbgs() << "RegClass: " << TRC->getName() << ' '); + dbgs() << "RegClass: " << TRC->getName() << ' '; }); AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs); |
