summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* [X86] Fix crash on assert of non-simple type after type-legalizationAyman Musa2017-09-031-5/+7
| | | | | | | | | | The function combineShuffleToVectorExtend in DAGCombine might generate an illegal typed node after "legalize types" phase, causing assertion on non-simple type to fail afterwards. Adding a type check in case the combine is running after the type legalize pass. Differential Revision: https://reviews.llvm.org/D37330 llvm-svn: 312438
* [MIParser] Ensure getHexUint doesn't produce APInts with a bitwidth of 0Jessica Paquette2017-09-011-2/+5
| | | | | | | | | | | | | | | | | | | | | If getHexUint reads in a hex 0, it will create an APInt with a value of 0. The number of active bits on this APInt is used to calculate the bitwidth of Result. The number of active bits is defined as an APInt's bitwidth - its number of leading 0s. Since this APInt is 0, its bitwidth and number of leading 0s are equal. Thus, Result is constructed with a bitwidth of 0, triggering an APInt assert. This commit fixes that by checking if the APInt is equal to 0, and setting the bitwidth to 32 if it is. Otherwise, it sets the bitwidth using getActiveBits. This caused issues when compiling MIR files with successor probabilities. In the case that a successor is tagged with a probability of 0, this assert would fire on debug builds. https://reviews.llvm.org/D37401 llvm-svn: 312387
* LiveIntervalAnalysis: Fix alias regunit reserved definitionMatthias Braun2017-09-013-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A register in CodeGen can be marked as reserved: In that case we consider the register always live and do not use (or rather ignore) kill/dead/undef operand flags. LiveIntervalAnalysis however tracks liveness per register unit (not per register). We already needed adjustments for this in r292871 to deal with super/sub registers. However I did not look at aliased register there. Looking at ARM: FPSCR (regunits FPSCR, FPSCR~FPSCR_NZCV) aliases with FPSCR_NZCV (regunits FPSCR_NZCV, FPSCR~FPSCR_NZCV) hence they share a register unit (FPSCR~FPSCR_NZCV) that represents the aliased parts of the registers. This shared register unit was previously considered non-reserved, however given that we uses of the reserved FPSCR potentially violate some rules (like uses without defs) we should make FPSCR~FPSCR_NZCV reserved too and stop tracking liveness for it. This patch: - Defines a register unit as reserved when: At least for one root register, the root register and all its super registers are reserved. - Adjust LiveIntervals::computeRegUnitRange() for new reserved definition. - Add MachineRegisterInfo::isReservedRegUnit() to have a canonical way of testing. - Stop computing LiveRanges for reserved register units in HMEditor even with UpdateFlags enabled. - Skip verification of uses of reserved reg units in the machine verifier (this usually didn't happen because there would be no cached liverange but there is no guarantee for that and I would run into this case before the HMEditor tweak, so may as well fix the verifier too). Note that this should only affect ARMs FPSCR/FPSCR_NZCV registers today; aliased registers are rarely used, the only other cases are hexagons P0-P3/P3_0 and C8/USR pairs which are not mixing reserved/non-reserved registers in an alias. Differential Revision: https://reviews.llvm.org/D37356 llvm-svn: 312348
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-09-013-23/+580
| | | | | | | | | | | | | | | | | | | | | | | | | | | Issues addressed since original review: - Moved removal of dead instructions found by LiveIntervals::shrinkToUses() outside of loop iterating over instructions to avoid instructions being deleted while pointed to by iterator. - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. - The pass no longer forwards COPYs to physical register uses, since doing so can break code that implicitly relies on the physical register number of the use. - The pass no longer forwards COPYs to undef uses, since doing so can break the machine verifier by creating LiveRanges that don't end on a use (since the undef operand is not considered a use). [MachineCopyPropagation] Extend pass to do COPY source forwarding This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. llvm-svn: 312328
* Reland rL312315: [MergeICmps] MergeICmps is a new optimization pass that ↵Clement Courbet2017-09-011-0/+8
| | | | | | | | | | turns chains of integer Add missing header. This reverts commit 86dd6335cf7607af22f383a9a8e072ba929848cf. llvm-svn: 312322
* Debug info for variables whose type is shrinked to boolStrahinja Petrovic2017-09-011-0/+1
| | | | | | | | | | | | | This patch provides such debug information for integer variables whose type is shrinked to bool by providing dwarf expression which returns either constant initial value or other value. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D35994 llvm-svn: 312318
* Revert "[MergeICmps] MergeICmps is a new optimization pass that turns chains ↵Clement Courbet2017-09-011-8/+0
| | | | | | | | | | of integer" Break build This reverts commit d07ab866f7f88f81e49046d691a80dcd32d7198b. llvm-svn: 312317
* [MergeICmps] MergeICmps is a new optimization pass that turns chains of integerClement Courbet2017-09-011-0/+8
| | | | | | | | | | | | | | | | | comparisons into memcmp. Thanks to recent improvements in the LLVM codegen, the memcmp is typically inlined as a chain of efficient hardware comparisons. This typically benefits C++ member or nonmember operator==(). For now this is disabled by default until: - https://bugs.llvm.org/show_bug.cgi?id=33329 is complete - Benchmarks show that this is always useful. Differential Revision: https://reviews.llvm.org/D33987 llvm-svn: 312315
* [MachineOutliner] Recommit r312194, missed optimization remarksJessica Paquette2017-08-311-1/+36
| | | | | | | | | | | | | Before, this commit caused a buildbot failure: http://bb.pgr.jp/builders/test-llvm-i686-linux-RA/builds/6026/steps/test_llvm/logs/LLVM%20%3A%3A%20CodeGen__AArch64__machine-outliner-remarks.ll This was caused by the Key value in DiagnosticInfoOptimizationBase being deallocated before emitting the remarks defined in MachineOutliner.cpp. As of r312277 this should no longer be an issue. llvm-svn: 312280
* [DAGCombiner] Do a better job of ensuring we don't split elements when ↵Craig Topper2017-08-311-4/+7
| | | | | | combining an extract_subvector of a bitcasted build_vector. llvm-svn: 312253
* [codeview] Generalize DIExpression parsing to handle load chainsReid Kleckner2017-08-314-42/+46
| | | | | | | | | | | | | | | Summary: Hopefully this also clarifies exactly when and why we're rewriting certiain S_LOCALs using reference types: We're using the reference type to stand in for a zero-offset load. Reviewers: inglorion Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37309 llvm-svn: 312247
* Revert r311525: "[XRay][CodeGen] Use PIC-friendly code in XRay sleds; remove ↵Daniel Jasper2017-08-311-25/+28
| | | | | | | | synthetic references in .text" Breaks builds internally. Will forward repo instructions to author. llvm-svn: 312243
* Revert r312194: "[MachineOutliner] Add missed optimization remarks for the ↵Daniel Jasper2017-08-311-36/+1
| | | | | | | | | outliner." Breaks on buildbot: http://bb.pgr.jp/builders/test-llvm-i686-linux-RA/builds/6026/steps/test_llvm/logs/LLVM%20%3A%3A%20CodeGen__AArch64__machine-outliner-remarks.ll llvm-svn: 312219
* Temporarily revert "Update branch coalescing to be a PowerPC specific pass"Eric Christopher2017-08-314-0/+763
| | | | | | | | From comments and code review it wasn't intended to be enabled by default yet. This reverts commit r311588. llvm-svn: 312214
* [MachineOutliner] Add missed optimization remarks for the outliner.Jessica Paquette2017-08-301-1/+36
| | | | | | | | | | | | | | This adds missed optimization remarks which report viable candidates that were not outlined because they would increase code size. Other remarks will come in separate commits. This will help to diagnose code size regressions and changes in outliner behaviour in projects using the outliner. https://reviews.llvm.org/D37085 llvm-svn: 312194
* Revert r312154 "Re-enable "[MachineCopyPropagation] Extend pass to do COPY ↵Hans Wennborg2017-08-303-577/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | source forwarding"" It caused PR34387: Assertion failed: (RegNo < NumRegs && "Attempting to access record for invalid register number!") > Issues identified by buildbots addressed since original review: > - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. > - The pass no longer forwards COPYs to physical register uses, since > doing so can break code that implicitly relies on the physical > register number of the use. > - The pass no longer forwards COPYs to undef uses, since doing so > can break the machine verifier by creating LiveRanges that don't > end on a use (since the undef operand is not considered a use). > > [MachineCopyPropagation] Extend pass to do COPY source forwarding > > This change extends MachineCopyPropagation to do COPY source forwarding. > > This change also extends the MachineCopyPropagation pass to be able to > be run during register allocation, after physical registers have been > assigned, but before the virtual registers have been re-written, which > allows it to remove virtual register COPY LiveIntervals that become dead > through the forwarding of all of their uses. llvm-svn: 312178
* SelectionDAG: Emit correct debug info for multi-register function arguments.Adrian Prantl2017-08-301-0/+21
| | | | | | | | | Previously we would just describe the first register and then call it quits. This patch emits fragment expressions for each register. <rdar://problem/34075307> llvm-svn: 312169
* Refactor DIBuilder::createFragmentExpression into a static DIExpression memberAdrian Prantl2017-08-301-11/+8
| | | | | | NFC llvm-svn: 312165
* [GISel]: Add a clean up combiner during legalization.Aditya Nandakumar2017-08-301-101/+60
| | | | | | | | | | | Added a combiner which can clean up truncs/extends that are created in order to make the types work during legalization. Also moved the combineMerges to the LegalizeCombiner. https://reviews.llvm.org/D36880 llvm-svn: 312158
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-08-303-23/+577
| | | | | | | | | | | | | | | | | | | | | | | Issues identified by buildbots addressed since original review: - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. - The pass no longer forwards COPYs to physical register uses, since doing so can break code that implicitly relies on the physical register number of the use. - The pass no longer forwards COPYs to undef uses, since doing so can break the machine verifier by creating LiveRanges that don't end on a use (since the undef operand is not considered a use). [MachineCopyPropagation] Extend pass to do COPY source forwarding This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. llvm-svn: 312154
* [codeview] make DbgVariableLocation::extractFromMachineInstruction use OptionalBob Haarman2017-08-303-29/+31
| | | | | | | | | | | | | | | | Summary: DbgVariableLocation::extractFromMachineInstruction originally returned a boolean indicating success. This change makes it return an Optional<DbgVariableLocation> so we cannot try to access the fields of the struct if they aren't valid. Reviewers: aprantl, rnk, zturner Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37279 llvm-svn: 312143
* Re-land MachineInstr: Reason locally about some memory objects before going ↵Balaram Makam2017-08-301-17/+43
| | | | | | | | | | | | | | | | | | | | to AA. Summary: Reverts r311008 to reinstate r310825 with a fix. Refine alias checking for pseudo vs value to be conservative. This fixes the original failure in builtbot unittest SingleSource/UnitTests/2003-07-09-SignedArgs. Reviewers: hfinkel, nemanjai, efriedma Reviewed By: efriedma Subscribers: bjope, mcrosier, nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36900 llvm-svn: 312126
* [codeview] add missing break in CodeGen/AsmPrinter/DebugHandlerBase.cppBob Haarman2017-08-291-0/+1
| | | | llvm-svn: 312055
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-298-180/+332
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 312053
* [NFC] clang-format llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cppBob Haarman2017-08-291-2/+4
| | | | llvm-svn: 312035
* Reland r311957 [codeview] support more DW_OPs for more complete debug infoBob Haarman2017-08-294-86/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Some variables show up in Visual Studio as "optimized out" even in -O0 -Od builds. This change fixes two issues that would cause this to happen. The first issue is that not all DIExpressions we generate were recognized by the CodeView writer. This has been addressed by adding support for DW_OP_constu, DW_OP_minus, and DW_OP_plus. The second issue is that we had no way to encode DW_OP_deref in CodeView. We get around that by changinge the type we encode in the debug info to be a reference to the type in the source code. This fixes PR34261. The reland adds two extra checks to the original: It checks if the DbgVariableLocation is valid before checking any of its fields, and it only emits ranges with nonzero registers. Reviewers: aprantl, rnk, zturner Reviewed By: rnk Subscribers: mgorny, llvm-commits, aprantl, hiraditya Differential Revision: https://reviews.llvm.org/D36907 llvm-svn: 312034
* [DAG] Bound loop dependence check in merge optimization.Hans Wennborg2017-08-291-5/+17
| | | | | | | | | | | | | The loop dependence check looks for dependencies between store merge candidates not captured by the chain sub-DAG doing a check of predecessors which may be very large. Conservatively bound number of nodes checked for compilation time. (Resolves PR34326). Landing on behalf of Nirav Dave to unblock the 5.0.0 release. Differential Revision: https://reviews.llvm.org/D37220 llvm-svn: 312022
* [Instruction] add moveAfter() convenience function; NFCISanjay Patel2017-08-292-14/+5
| | | | | | | | | As suggested in D37121, here's a wrapper for removeFromParent() + insertAfter(), but implemented using moveBefore() for symmetry/efficiency. Differential Revision: https://reviews.llvm.org/D37239 llvm-svn: 312001
* Revert "[codeview] support more DW_OPs for more complete debug info"Bob Haarman2017-08-294-192/+86
| | | | | | This reverts commit e160912f53f047bc97e572add179e08e33f4df48. llvm-svn: 311977
* Revert "[codeview] don't try to emit variable locations without registers"Bob Haarman2017-08-291-1/+1
| | | | | | This reverts commit a256fbcacf448ee793d23552c46ed2971bf9eff5. llvm-svn: 311976
* [codeview] don't try to emit variable locations without registersBob Haarman2017-08-291-1/+1
| | | | | | | This fixes a problem introduced 311957, where the compiler would crash with "fatal error: error in backend: unknown codeview register". llvm-svn: 311969
* [codeview] support more DW_OPs for more complete debug infoBob Haarman2017-08-294-86/+192
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Some variables show up in Visual Studio as "optimized out" even in -O0 -Od builds. This change fixes two issues that would cause this to happen. The first issue is that not all DIExpressions we generate were recognized by the CodeView writer. This has been addressed by adding support for DW_OP_constu, DW_OP_minus, and DW_OP_plus. The second issue is that we had no way to encode DW_OP_deref in CodeView. We get around that by changinge the type we encode in the debug info to be a reference to the type in the source code. This fixes PR34261. Reviewers: aprantl, rnk, zturner Reviewed By: rnk Subscribers: mgorny, llvm-commits, aprantl, hiraditya Differential Revision: https://reviews.llvm.org/D36907 llvm-svn: 311957
* Fix a logic error in DwarfExpression::addMachineReg()Adrian Prantl2017-08-281-4/+3
| | | | | | | | | This fixes PR34323 and thus splitting undescribable registers into smaller, describable sub-registers. https://bugs.llvm.org/show_bug.cgi?id=34323 llvm-svn: 311951
* [CodeView] Don't output S_UDT symbols for forward decls.Zachary Turner2017-08-282-16/+35
| | | | | | | | | | | | | | | | | | | | | | S_UDT symbols are the debugger's "index" for all the structs, typedefs, classes, and enums in a program. If any of those structs/classes don't have a complete declaration, or if there is a typedef to something that doesn't have a complete definition, then emitting the S_UDT is unhelpful because it doesn't give the debugger enough information to do anything useful. On the other hand, it results in a huge size blow-up in the resulting PDB, which is exacerbated by an order of magnitude when linking with /DEBUG:FASTLINK. With this patch, we drop S_UDT records for types that refer either directly or indirectly (e.g. through a typedef, pointer, etc) to a class/struct/union/enum without a complete definition. This brings us about 50% of the way towards parity with /DEBUG:FASTLINK PDBs generated from cl-compiled object files. Differential Revision: https://reviews.llvm.org/D37162 llvm-svn: 311904
* [DAGCombiner] Teach visitEXTRACT_SUBVECTOR to turn extracts of BUILD_VECTOR ↵Craig Topper2017-08-281-0/+23
| | | | | | | | | | into smaller BUILD_VECTORs Only do this before operations are legalized of BUILD_VECTOR is Legal for the target. Differential Revision: https://reviews.llvm.org/D37186 llvm-svn: 311892
* Untabify.NAKAMURA Takumi2017-08-282-6/+6
| | | | llvm-svn: 311875
* [DAGCombiner] allow undef shuffle operands when eliminating bitcasts (PR34111)Sanjay Patel2017-08-271-1/+4
| | | | | | | | As noted in the FIXME, this could be improved more, but this is the smallest fix that helps: https://bugs.llvm.org/show_bug.cgi?id=34111 llvm-svn: 311853
* [DAGCombiner] Extending pattern detection for vector shuffle.Jatin Bhateja2017-08-261-3/+53
| | | | | | | | | | | | | | | | | | Summary: If all the operands of a BUILD_VECTOR extract elements from same vector then split the vector efficiently based on the maximum vector access index. This will also fix PR 33784 Reviewers: zvi, delena, RKSimon, thakis Reviewed By: RKSimon Subscribers: chandlerc, eladcohen, llvm-commits Differential Revision: https://reviews.llvm.org/D35788 llvm-svn: 311833
* Revert rL311247 : To rectify commit message.Jatin Bhateja2017-08-261-53/+3
| | | | | | | | Summary: This reverts commit rL311247. Differential Revision: https://reviews.llvm.org/D36927 llvm-svn: 311832
* Add options to dump block frequency/branch probability info in text.Hiroshi Yamauchi2017-08-261-0/+13
| | | | | | | | | | | | | | | | | | | | | Summary: Add options -print-bfi/-print-bpi that dump block frequency and branch probability info like -view-block-freq-propagation-dags and -view-machine-block-freq-propagation-dags do but in text. This is useful when the graph is very large and complex (the dot command crashes, lines/edges too close to tell apart, hard to navigate without textual search) or simply when text is preferred. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37165 llvm-svn: 311822
* Fix unused-lambda-capture warning by using default capture-by-refDavid Blaikie2017-08-251-2/+1
| | | | | | | | Since the lambda isn't escaped (via a std::function or similar) it's fine/better to use default capture-by-ref to provide semantics similar to language-level nested scopes (if/for/while/etc). llvm-svn: 311782
* Fix buildbot breakage from r311763. Remove unused lambda capture.Matt Morehouse2017-08-251-2/+1
| | | | llvm-svn: 311781
* [GISel]: Implement widenScalar for Legalizing G_PHIAditya Nandakumar2017-08-252-14/+47
| | | | | | https://reviews.llvm.org/D37018 llvm-svn: 311763
* [DAG] convert vector select-of-constants to logic/mathSanjay Patel2017-08-241-2/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | This goes back to a discussion about IR canonicalization. We'd like to preserve and convert more IR to 'select' than we currently do because that's likely the best choice in IR: http://lists.llvm.org/pipermail/llvm-dev/2016-September/105335.html ...but that's often not true for codegen, so we need to account for this pattern coming in to the backend and transform it to better DAG ops. Steps in this patch: 1. Add an EVT param to the existing convertSelectOfConstantsToMath() TLI hook to more finely enable this transform. Other targets will probably want that anyway to distinguish scalars from vectors. We're using that here to exclude AVX512 targets, but it may not be necessary. 2. Convert a vselect to ext+add. This eliminates a constant load/materialization, and the vector ext is often free. Implementing a more general fold using xor+and can be a follow-up for targets that don't have a legal vselect. It's also possible that we can remove the TLI hook for the special case fold implemented here because we're eliminating a constant, but it needs to be tested on other targets. Differential Revision: https://reviews.llvm.org/D36840 llvm-svn: 311731
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-2410-172/+312
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 311703
* Remove duplicate codeVictor Leschuk2017-08-241-4/+0
| | | | llvm-svn: 311675
* Add missing break in switchVictor Leschuk2017-08-241-0/+1
| | | | llvm-svn: 311673
* IPRA: Don't assume called function is first call operandMatt Arsenault2017-08-241-8/+20
| | | | | | | | Fixes not finding the called global for AMDGPU call pseudoinstructions, which prevented IPRA from doing much. llvm-svn: 311637
* IPRA: Exit early on functions without callsMatt Arsenault2017-08-241-0/+5
| | | | llvm-svn: 311636
* Add ‘llvm.experimental.constrained.fma‘ Intrinsic.Wei Ding2017-08-243-3/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D36335 llvm-svn: 311629
OpenPOWER on IntegriCloud