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* Refactor the code that checks that all operands of a node are UNDEFs.Nadav Rotem2012-07-152-13/+28
| | | | | | | | | Add a micro-optimization to getNode of CONCAT_VECTORS when both operands are undefs. Can't find a testcase for this because VECTOR_SHUFFLE already handles undef operands, but Duncan suggested that we add this. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160229
* Reapply r160194, switching to use LV information for finding local kills.Chandler Carruth2012-07-151-56/+32
| | | | | | | | | | | | | | | | | | | | | The notable fix is to look at any dependencies attached to the kill instruction (or other instructions between MI nad the kill) where the dependencies are specific to the register in question. The old code implicitly handled this by rejecting the transform if *any* other uses were found within the block, but after the start point. The new code directly finds the kill, and has to re-use the existing dependency scan to check for non-kill uses. This was caught by self-host, but I found the bug via inspection and use of absurd assert scaffolding to compute the kills in two ways and compare them. So I have no useful testcase for this other than "bootstrap". I'd work harder to reduce a test case if this particular code were likely to live for a long time. Thanks to Benjamin Kramer for reviewing the fix itself. llvm-svn: 160228
* Add a dagcombine optimization to convert concat_vectors of undefs into a ↵Nadav Rotem2012-07-141-0/+11
| | | | | | | | single undef. The unoptimized concat_vectors isd prevented the canonicalization of the vector_shuffle node. llvm-svn: 160221
* Account for early-clobber reload instructions.Jakob Stoklund Olesen2012-07-141-0/+4
| | | | | | No test case, there are no in-tree targets that require this. llvm-svn: 160219
* Be more verbose when detecting dominance problems.Jakob Stoklund Olesen2012-07-132-7/+29
| | | | | | | | | | Catch uses of undefined physregs that haven't been added to basic block live-in lists. Run the verifier to pinpoint the problem. Also run the verifier when a virtual register use is not jointly dominated by defs. llvm-svn: 160207
* Revert r160194, which switched to use LV information for finding localChandler Carruth2012-07-131-19/+54
| | | | | | | | kills. This is causing miscompiles that I'm working on tracking down. llvm-svn: 160196
* Use the LiveVariables information to efficiently get local kills. ThisChandler Carruth2012-07-131-54/+19
| | | | | | | | | | removes the largest scaling problem in the test cases from PR13225 when ASan is switched to insert basic blocks in the natural CFG order. It may also solve some scaling problems for more normal code with large numbers of basic blocks and variables. llvm-svn: 160194
* Provide function name in 'Cannot select' fatal error.Jim Grosbach2012-07-131-0/+1
| | | | | | | | | When dumping the DAG for a fatal 'Cannot select' back-end error, also provide the name of the function the construct is in. Useful when dealing with large testcases, as the next step is to llvm-extract the function in question to get a small(er) testcase. llvm-svn: 160152
* The end of the prologue should be marked with is_stmt.Eric Christopher2012-07-121-1/+1
| | | | | | | | Fixes PR13303. Patch by Paul Robinson! llvm-svn: 160148
* The result type of EXTRACT_VECTOR_ELT doesn't have to match the element type ofDuncan Sands2012-07-121-0/+10
| | | | | | | | | the input vector, it can be bigger (this is helpful for powerpc where <2 x i16> is a legal vector type but i16 isn't a legal type, IIRC). However this wasn't being taken into account by ExpandRes_EXTRACT_VECTOR_ELT, causing PR13220. Lightly tweaked version of a patch by Michael Liao. llvm-svn: 160116
* InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:Evan Cheng2012-07-111-1/+2
| | | | | | | | | | | | | | | | | r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to a copy: r1026 = copy r1024 This is correct. However it uses TII->isCoalescableExtInstr() which can return true for instructions which essentially does a sext_in_reg so this can end up with an illegal copy where the source and destination register classes do not match. Add a check to avoid it. Sorry, no test case possible at this time. rdar://11849816 llvm-svn: 160059
* Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, ↵Nadav Rotem2012-07-111-100/+104
| | | | | | | | Ptr, etc. No functionality change. llvm-svn: 160042
* Remove unused variable.Benjamin Kramer2012-07-111-2/+0
| | | | llvm-svn: 160040
* Refactor the DAG Legalizer by extracting the legalization ofNadav Rotem2012-07-111-422/+434
| | | | | | | Load and Store nodes into their own functions. No functional change. llvm-svn: 160037
* Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns ↵Owen Anderson2012-07-111-1/+2
| | | | | | | | an MVT::i1, i.e. before type legalization. This is a speculative fix for a problem on Mips reported by Akira Hatanaka. llvm-svn: 160036
* Require and preserve LoopInfo for early if-conversion.Jakob Stoklund Olesen2012-07-101-0/+17
| | | | | | It will surely be needed by heuristics. llvm-svn: 160027
* Teach the LiveInterval::join function to use the fast merge algorithm,Chandler Carruth2012-07-101-14/+17
| | | | | | | | | | | generalizing its implementation sufficiently to support this value number scenario as well. This cuts out another significant performance hit in large functions (over 10k basic blocks, etc), especially those with "natural" CFG structures. llvm-svn: 160026
* Run early if-conversion in domtree post-order.Jakob Stoklund Olesen2012-07-101-49/+60
| | | | | | | | | | | This ordering allows nested if-conversion without using a work list, and it makes it possible to update the dominator tree on the fly as well. Any erased basic blocks will always be dominated by the current post-order position, so the domtree can be pruned without invalidating the iterator. llvm-svn: 160025
* Fix a bug where I didn't test for an empty range before inspecting theChandler Carruth2012-07-101-1/+2
| | | | | | | | | | | | | | | back of it. I don't have anything even remotely close to a test case for this. It only broke two build bots, both of them doing bootstrap builds, one of them a dragonegg bootstrap. It doesn't break for me when I bootstrap either. It doesn't reproduce every time or on many machines during the bootstrap. Many thanks to Duncan Sands who got the exact command (and stage of the bootstrap) which failed on the dragonegg bootstrap and managed to get it to trigger under valgrind with debug symbols. The fix was then found by inspection. llvm-svn: 159993
* Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem2012-07-101-1/+1
| | | | | | | | | multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. llvm-svn: 159991
* Add an efficient merge operation to LiveInterval and use it to avoidChandler Carruth2012-07-101-32/+132
| | | | | | | | | | | quadratic behavior when performing pathological merges. Fixes the core element of PR12652. There is only one user of addRangeFrom left: join. I'm hoping to refactor further in a future patch and have join use this merge operation as well. llvm-svn: 159982
* Teach LiveIntervals how to verify themselves and start using it in someChandler Carruth2012-07-101-0/+33
| | | | | | | | | | of the trick merge routines. This adds a layer of testing that was necessary when implementing more efficient (and complex) merge logic for this datastructure. No functionality changed here. llvm-svn: 159981
* indentationAndrew Trick2012-07-091-1/+1
| | | | llvm-svn: 159958
* Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional ↵Owen Anderson2012-07-091-0/+36
| | | | | | | | move, since there are only two possible values. Previously, this would become an integer extension operation, followed by a real integer->float conversion. llvm-svn: 159957
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-074-6/+9
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* Whitespace.Chad Rosier2012-07-061-3/+3
| | | | llvm-svn: 159839
* [fast-isel] Tell fast-isel to do nothing with the new donothing intrinsic.Chad Rosier2012-07-061-0/+3
| | | | llvm-svn: 159837
* Fix PR13202 and a regtest.Alexey Samsonov2012-07-061-0/+6
| | | | | | | | | | | | | DwarfDebug class could generate the same (inlined) DIVariable twice: 1) when trying to find abstract debug variable for a concrete inlined instance. 2) when explicitly collecting info for variables that were optimized out. This change makes sure that this duplication won't happen and makes Clang pass "gdb.opt/inline-locals" test from gdb testsuite. Reviewed by Eric Christopher. llvm-svn: 159811
* Add some comments suggested in code review.Jakob Stoklund Olesen2012-07-061-0/+7
| | | | llvm-svn: 159800
* Optimize extendIntervalEndTo a tiny bit by saving one call through theChandler Carruth2012-07-051-7/+7
| | | | | | vector erase. No functionality changed. llvm-svn: 159746
* Finish fixing the MachineOperand hashing, providing a nice modernChandler Carruth2012-07-051-47/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | hash_value overload for MachineOperands. This addresses a FIXME sufficient for me to remove it, and cleans up the code nicely too. The important changes to the hashing logic: - TargetFlags are now included in all of the hashes. These were complete missed. - Register operands have their subregisters and whether they are a def included in the hash. - We now actually hash all of the operand types. Previously, many operand types were simply *dropped on the floor*. For example: - Floating point immediates - Large integer immediates (>64-bit) - External globals! - Register masks - Metadata operands - It removes the offset from the block-address hash; I'm a bit suspicious of this, but isIdenticalTo doesn't consider the offset for black addresses. Any patterns involving these entities could have triggered extreme slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs you think might be closed now... I'm looking myself, but I may miss them. llvm-svn: 159743
* All cases are covered, no need for a default. This deals with theDuncan Sands2012-07-051-1/+0
| | | | | | corresponding clang warning. llvm-svn: 159742
* The hash function for MI expressions, used by MachineCSE, is reallyChandler Carruth2012-07-051-3/+8
| | | | | | | | | | | | | | | | | | | | | broken. This patch fixes the superficial problems which lead to the intractably slow compile times reported in PR13225. The specific issue is that we were failing to include the *offset* of a global variable in the hash code. Oops. This would in turn cause all MIs which were only distinguishable due to operating on different offsets of a global variable to produce identical hash functions. In some of the test cases attached to the PR I saw hash table activity where there were O(1000) probes-per-lookup *on average*. A very few entries were responsible for most of these probes. There is still quite a bit more to do here. The ad-hoc layering of data in MachineOperands makes them *extremely* brittle to hash correctly. We're missing quite a few other cases, the only ones I've fixed here are the specific MO types which were allowed through the assert() in getOffset(). llvm-svn: 159741
* Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1Duncan Sands2012-07-051-9/+17
| | | | | | booleans. Patch by James Benton. llvm-svn: 159739
* Remove ParentMap. You can just ask the domnode for its parent. No functionalityNick Lewycky2012-07-051-11/+8
| | | | | | | | | | change. Move the "Not profitable, avoid CSE!" debug message next to where we fail the check for profitability and use a different message for avoiding CSE due to being in different register classes. llvm-svn: 159729
* Allow trailing physreg RegisterSDNode operands on non-variadic instructions.Jakob Stoklund Olesen2012-07-043-14/+30
| | | | | | | | | | | | | | | Also allow trailing register mask operands on non-variadic both MachineSDNodes and MachineInstrs. The extra physreg RegisterSDNode operands are added to the MI as <imp-use> operands. This makes it possible to have non-variadic call instructions. Call and return instructions really are non-variadic, the argument registers should only be used implicitly - they are not part of the encoding. llvm-svn: 159727
* Print SlotIndexes when available for -print-machineinstrs.Jakob Stoklund Olesen2012-07-041-1/+2
| | | | llvm-svn: 159726
* Allow multiple terminators to read virtual registers.Jakob Stoklund Olesen2012-07-041-33/+29
| | | | | | | | Find the kill as the last terminator to read SrcReg. Patch by Philipp Brüschweiler! llvm-svn: 159722
* Make sure -print-machineinstrs applies to the first pass as well.Jakob Stoklund Olesen2012-07-041-3/+3
| | | | llvm-svn: 159720
* Reverted r156659, due to probable performance regressions, DenseMap should ↵Stepan Dyatkovskiy2012-07-041-8/+7
| | | | | | | | | | be used here: IntegersSubsetMapping - Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement if possible. llvm-svn: 159703
* Reduce some code duplication.Eric Christopher2012-07-041-19/+4
| | | | llvm-svn: 159701
* Fix some ascii art in a comment to not have trailing backslashes (inspirationMatt Beaumont-Gay2012-07-041-5/+5
| | | | | | | from IfConversion.cc), and fix some spelling and grammar in the surrounding prose. llvm-svn: 159699
* Add an experimental early if-conversion pass, off by default.Jakob Stoklund Olesen2012-07-044-0/+594
| | | | | | | | | | | | | This pass performs if-conversion on SSA form machine code by speculatively executing both sides of the branch and using a cmov instruction to select the result. This can help lower the number of branch mispredictions on architectures like x86 that don't have predicable instructions. The current implementation is very aggressive, and causes regressions on mosts tests. It needs good heuristics that have yet to be implemented. llvm-svn: 159694
* Part of r159527. Splitted into series of patches and gone with fixed PR13256:Stepan Dyatkovskiy2012-07-031-7/+8
| | | | | | | | IntegersSubsetMapping - Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement if possible. llvm-svn: 159659
* Revert "IntRange:" as it appears to be breaking self hosting.Eric Christopher2012-07-021-8/+7
| | | | | | This reverts commit b2833d9dcba88c6f0520cad760619200adc0442c. llvm-svn: 159618
* All glory to address sanitizer. ;]Chandler Carruth2012-07-021-2/+8
| | | | | | | | | | | | It appears to have caught a use-after-free introduced as by r159567 and/or friends which call 'addPass' from many more places. The bug in 'addPass' doesn't appear to be new, and was spotted by inspection when ASan shown a bright light of a stacktrace at these functions. Hopefully this will fix the ASan failure -- I have no test case other than running an ASan-built clang over the test suite. llvm-svn: 159614
* Target option DisableJumpTables is a gross hack. Move it to TargetLowering ↵Evan Cheng2012-07-022-1/+2
| | | | | | instead. llvm-svn: 159611
* misched: allow NULL InstrItineraries.Andrew Trick2012-07-021-0/+1
| | | | llvm-svn: 159599
* Turn an assert into an error to make it a bit more friendly.Eric Christopher2012-07-021-2/+9
| | | | | | Part of rdar://6880388 and rdar://11766377 llvm-svn: 159590
* Extend TargetPassConfig to allow running only a subset of the normal passes.Bob Wilson2012-07-022-8/+37
| | | | | | | | | | | | | | | | | This is still a work in progress but I believe it is currently good enough to fix PR13122 "Need unit test driver for codegen IR passes". For example, you can run llc with -stop-after=loop-reduce to have it dump out the IR after running LSR. Serializing machine-level IR is not yet supported but we have some patches in progress for that. The plan is to serialize the IR to a YAML file, containing separate sections for the LLVM IR, machine-level IR, and whatever other info is needed. Chad suggested that we stash the stop-after pass in the YAML file and use that instead of the start-after option to figure out where to restart the compilation. I think that's a great idea, but since it's not implemented yet I put the -start-after option into this patch for testing purposes. llvm-svn: 159570
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