summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Fix a bug introduced with my previous patch, where it didn't correctly handleChris Lattner2007-04-091-7/+9
| | | | | | | instructions which replace themselves when FI's are rewritten (common on ppc). This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll llvm-svn: 35789
* Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308:Chris Lattner2007-04-091-1/+5
| | | | | | | some instructions can have multiple frame indices in them. If this happens, rewrite all of them. llvm-svn: 35785
* Fix PR1316Chris Lattner2007-04-091-4/+4
| | | | llvm-svn: 35783
* Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314Chris Lattner2007-04-081-1/+1
| | | | llvm-svn: 35779
* minor comment fixChris Lattner2007-04-061-1/+1
| | | | llvm-svn: 35696
* Change the bit_part_select (non)implementation from "return 0" to abort.Reid Spencer2007-04-051-3/+5
| | | | llvm-svn: 35679
* Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.Reid Spencer2007-04-042-0/+180
| | | | llvm-svn: 35678
* Properly emit range comparisons for switch cases, where neighbour casesAnton Korobeynikov2007-04-041-71/+181
| | | | | | | go to the same destination. Now we're producing really good code for switch-lower-feature.ll testcase llvm-svn: 35672
* Re-materialize all loads from fixed stack slots.Evan Cheng2007-04-043-15/+34
| | | | llvm-svn: 35660
* Trivially re-materializable instructions have spill weights that are half of ↵Evan Cheng2007-04-041-6/+6
| | | | | | what it would be otherwise. llvm-svn: 35658
* Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found.Evan Cheng2007-04-031-1/+1
| | | | llvm-svn: 35618
* 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.Scott Michel2007-04-022-25/+76
| | | | | | | | | 2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL patterns. This was motivated by the X86/rotate.ll testcase, which should now generate code for other platforms (and soon-to-come platforms.) Rewrote code slightly to make it easier to read. llvm-svn: 35605
* Ugh. Copy coalescer does not update register numbers.Evan Cheng2007-04-021-2/+15
| | | | llvm-svn: 35600
* For PR1297:Reid Spencer2007-04-021-1/+1
| | | | | | | Make sure that the CTPOP result is casted to i32 as the bit counting intrinsics all return i32 now (this affects CTLZ and CTTZ as well). llvm-svn: 35567
* For PR1297:Reid Spencer2007-04-011-17/+4
| | | | | | Support overloaded intrinsics bswap, ctpop, cttz, ctlz. llvm-svn: 35547
* For PR1297:Reid Spencer2007-04-011-24/+31
| | | | | | | Adjust for changes in the bit counting intrinsics. They all return i32 now so we have to trunc/zext the DAG node accordingly. llvm-svn: 35546
* For PR1297:Reid Spencer2007-04-011-1/+1
| | | | | | Change getOperationName to return std::string instead of const char* llvm-svn: 35545
* move a bunch of code out of the sdisel pass into its own opt pass ↵Chris Lattner2007-03-312-485/+21
| | | | | | "codegenprepare". llvm-svn: 35529
* switch TL::getValueType to use MVT::getValueType.Chris Lattner2007-03-311-22/+0
| | | | llvm-svn: 35527
* Add a -print-lsr-output option to LLC, to print the output of the LSR pass.Chris Lattner2007-03-311-1/+9
| | | | llvm-svn: 35522
* add one addressing mode description hook to rule them all.Chris Lattner2007-03-301-0/+34
| | | | llvm-svn: 35520
* Fix incorrect combination of different loads. Reenable zext-over-truncateDale Johannesen2007-03-302-75/+71
| | | | | | combination. llvm-svn: 35517
* Don't add the same MI to register reuse "last def/use" twice if it reads theEvan Cheng2007-03-301-1/+4
| | | | | | register more than once. llvm-svn: 35513
* Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep lengthEvan Cheng2007-03-301-5/+10
| | | | | | | | of dead def live interval at 1 to avoid multiple def's targeting the same register. The previous patch missed a case where the source operand is live-in. In that case, remove the whole interval. llvm-svn: 35512
* Disable load width reduction xform of variant (zext (truncate load x)) forEvan Cheng2007-03-291-1/+3
| | | | | | big endian targets until llvm-gcc build issue has been resolved. llvm-svn: 35449
* New entries.Evan Cheng2007-03-291-0/+21
| | | | llvm-svn: 35445
* Notes on re-materialization.Evan Cheng2007-03-281-0/+40
| | | | llvm-svn: 35420
* Move rematerialization out of beta.Evan Cheng2007-03-281-7/+1
| | | | llvm-svn: 35419
* Scale 1 is always ok.Evan Cheng2007-03-281-1/+1
| | | | llvm-svn: 35407
* Remove isLegalAddressImmediate.Evan Cheng2007-03-281-8/+0
| | | | llvm-svn: 35406
* GEP index sinking fixes:Evan Cheng2007-03-281-40/+35
| | | | | | | | | 1) Take address scale into consideration. e.g. i32* -> scale 4. 2) Examine all the users of GEP. 3) Generalize to inter-block GEP's (no longer uses loopinfo). 4) Don't do xform if GEP has other variable index(es). llvm-svn: 35403
* Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing shouldEvan Cheng2007-03-281-3/+5
| | | | | | not violate that. llvm-svn: 35396
* Remove dead codeAnton Korobeynikov2007-03-271-82/+46
| | | | llvm-svn: 35380
* Split big monster into small helpers. No functionality change.Anton Korobeynikov2007-03-271-190/+285
| | | | llvm-svn: 35379
* SDISel does not preserve all, it changes CFG and other info.Evan Cheng2007-03-271-1/+0
| | | | llvm-svn: 35376
* Don't call getOperandConstraint() if operand index is greater thanEvan Cheng2007-03-271-1/+2
| | | | | | TID->numOperands. llvm-svn: 35375
* Fix for PR1266. Don't mark a two address operand IsKill.Evan Cheng2007-03-262-22/+33
| | | | llvm-svn: 35365
* Change findRegisterUseOperand() to return operand index instead.Evan Cheng2007-03-261-4/+4
| | | | llvm-svn: 35363
* Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable toDale Johannesen2007-03-261-15/+15
| | | | | | hopefully forestall similar errors. llvm-svn: 35362
* SIGN_EXTEND_INREG requires one extra operand, a ValueType node.Evan Cheng2007-03-261-2/+6
| | | | llvm-svn: 35350
* First step of switch lowering refactoring: perform worklist-drivenAnton Korobeynikov2007-03-251-176/+249
| | | | | | strategy, emit JT's where possible. llvm-svn: 35338
* Implement support for vector operands to inline asm, implementingChris Lattner2007-03-251-4/+16
| | | | | | CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll llvm-svn: 35332
* implement initial support for the silly X constraint. Testcase here: ↵Chris Lattner2007-03-251-0/+2
| | | | | | CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll llvm-svn: 35327
* Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.llChris Lattner2007-03-251-1/+4
| | | | llvm-svn: 35324
* switch TargetLowering::getConstraintType to take the entire constraint,Chris Lattner2007-03-252-24/+28
| | | | | | not just the first letter. No functionality change. llvm-svn: 35322
* don't rely on ADLChris Lattner2007-03-241-1/+1
| | | | llvm-svn: 35299
* Adjust offset to compensate for big endian machines.Evan Cheng2007-03-241-7/+5
| | | | llvm-svn: 35293
* Make sure SEXTLOAD of the specific type is supported on the target.Evan Cheng2007-03-231-0/+4
| | | | llvm-svn: 35289
* Also replace uses of SRL if that's also folded during ReduceLoadWidth().Evan Cheng2007-03-231-1/+8
| | | | llvm-svn: 35286
* A couple of bug fixes for reducing load width xform:Evan Cheng2007-03-231-7/+16
| | | | | | | 1. Address offset is in bytes. 2. Make sure truncate node uses are replaced with new load. llvm-svn: 35274
OpenPOWER on IntegriCloud