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* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-012-9/+25
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-0/+6
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* [AArch64][GlobalISel] Zero-extend s1 values when returning.Amara Emerson2018-06-011-11/+1
| | | | | | | | | | | Before we were relying on the any extend of the s1 to s32, but for AAPCS we need to zero-extend it to at least s8. Fixes PR36719 Differential Revision: https://reviews.llvm.org/D47425 llvm-svn: 333747
* NFC Avoid a warning in WasmEHPrepare.cppGabor Buella2018-06-011-1/+1
| | | | | | | | | | ``` ../lib/CodeGen/WasmEHPrepare.cpp:166:30: warning: extra ‘;’ [-Wpedantic] false, false); ^ ``` llvm-svn: 333732
* Change ambiguous uses of term 'funclet' to 'EH scopes'. NFC.Heejin Ahn2018-06-014-48/+51
| | | | | | | | | | | | | | | | | | Summary: `getEHScopeMembership()` function is used not only for funclet-based EHs; they apply to all EH schemes that use the scoped IR (catchpad/cleanuppad/...). D47005 (rL333045) changed some of the uses of the term 'funclet' to 'EH scopes' in case they apply to all scoped EH, and this fixes more of them. For `FuncletLayout` pass, I left it as is because the pass is only used for funclet-based EH. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47611 llvm-svn: 333711
* [WebAssembly] Support instruction selection for catching exceptionsHeejin Ahn2018-05-311-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This lowers exception catching-related instructions: 1. Lowers `wasm.catch` intrinsic to `catch` instruction 2. Removes `catchpad` and `cleanuppad` instructions; they are not necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or `MachineBasicBlock::isEHPad()` can be used instead.) 3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret` and `cleanupret` instructions in isel, which will be replaced with other instructions in `WebAssemblyExceptionPrepare` pass. 4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various transformation for EH. Currently this pass only replaces `catchret` and `cleanupret` instructions into appropriate wasm instructions to make this patch successfully run until the end. Currently this does not handle lowering of intrinsics related to LSDA info generation (`wasm.landingpad.index` and `wasm.lsda`), because they cannot be tested without implementing `EHStreamer`'s wasm-specific handlers. They are marked as TODO, which is needed to make isel pass. Also this does not generate `try` and `end_try` markers yet, which will be handled in later patches. This patch is based on the first wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D44090 llvm-svn: 333705
* [WebAssembly] Add Wasm exception handling prepare passHeejin Ahn2018-05-315-6/+358
| | | | | | | | | | | | | | | | Summary: This adds a pass that transforms a program to be prepared for Wasm exception handling. This is using Windows EH instructions and based on the previous Wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, mgorny, sbc100, jgravelle-google, JDevlieghere, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D43746 llvm-svn: 333696
* [ADT] Make escaping fn conform to coding guidelinesJonas Devlieghere2018-05-311-1/+1
| | | | | | | | As noted by Adrian on llvm-commits, PrintHTMLEscaped and PrintEscaped in StringExtras did not conform to the LLVM coding guidelines. This commit rectifies that. llvm-svn: 333669
* [MCSchedule] Add the ability to compute the latency and throughput ↵Andrea Di Biagio2018-05-312-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | information for MCInst. This patch extends the MCSchedModel API with new methods that can be used to obtain the latency and reciprocal througput information for an MCInst. Scheduling models have recently gained the ability to resolve variant scheduling classes associated with MCInst objects. Before, models were only able to resolve a variant scheduling class from a MachineInstr object. This patch is mainly required by D47374 to avoid regressing a pair of x86 specific -print-schedule tests for btver2. Patch D47374 introduces a new variant class to teach the btver scheduling model (x86 target) how to correctly compute the latency profile for some zero-idioms using the new scheduling predicates. The new methods added by this patch would be mainly used by llc when flag -print-schedule is specified. In particular, tests that contain inline assembly require that code is parsed at code emission stage into a sequence of MCInst. That forces the print-schedule functionality to query the latency/rthroughput information for MCInst instructions too. If we don't expose this new API, then we lose "-print-schedule" test coverage as soon as variant scheduling classes are added to the x86 models. The tablegen SubtargetEmitter changes teaches how to query latency profile information using a object that derives from TargetSubtargetInfo. Note that this should really have been part of r333286. To avoid code duplication, the logic that "resolves" variant scheduling classes for MCInst, has been moved to a common place in MC. That logic is used by the "resolveVariantSchedClass" methods redefined in override by the tablegen'd GenSubtargetInfo classes. Differential Revision: https://reviews.llvm.org/D47536 llvm-svn: 333650
* [GlobalISel][Legalizer] LegalizerInfo verifier: Making ↵Roman Tereshin2018-05-311-0/+3
| | | | | | | | | | | | LegalizerInfo::verify(...) errors fatal Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333619
* [GlobalISel][Legalizer] LegalizerInfo verifier: check rules cover type indicesRoman Tereshin2018-05-301-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a simple verifier that tracks type indices being touched by legalization rules' builders. Every target will now have an opportunity to call LegalizerInfo::verify(...) at the end of its derived LegalizerInfo's constructor and check there are no obvious mistakes like checking only first type for an opcode that has more than one type index and therefore implicitly declaring any type for the second (and higher) type index legal. The check is only ran in assert builds and should have very minor performance impact in assert builds and none in release builds. This commit does not add LegalizerInfo::verify(...) calls to target-specific legalizers, look for separate commits for that. This commit also doesn't make the verification errors fatal, only produces an error message, look for a later commit that does. Reviewers: aemerson, qcolombet Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D46338 llvm-svn: 333576
* DAG: Remove redundant version of getRegisterTypeForCallingConvMatt Arsenault2018-05-291-4/+4
| | | | | | | | | | | There seems to be no real reason to have these separate copies. The existing implementations just copy each other for x86. For Mips there is a subtle difference, which is just a bug since it changes based on the context where which one was called. Dropping this version, all tests pass. If I try to merge them to match the removed version, a test fails. llvm-svn: 333440
* [StrictFP] Make getStrictFPOpcodeAction(...) more accessibleCameron McInally2018-05-291-32/+2
| | | | | | | | NFCI. This function will be reused in upcoming patches. Differential Revision: https://reviews.llvm.org/D47380 llvm-svn: 333433
* StackColoring: better handling of statically unreachable codeThan McIntosh2018-05-291-2/+5
| | | | | | | | | | | | | | | | Summary: Avoid assert/crash during liveness calculation in situations where the incoming machine function has statically unreachable BBs. Second attempt at submitting; this version of the change includes a revised testcase. Fixes PR37130. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47372 llvm-svn: 333416
* [CodeGenPrepare] Revert r331783Guozhi Wei2018-05-251-41/+0
| | | | | | The patch r331783 caused regression in one of our internal application. So revert it now, will investigate it further. llvm-svn: 333305
* [RegUsageInfoCollector] Bugfix for callee saved registers.Jonas Paulsson2018-05-251-11/+59
| | | | | | | | | | | | | | | | | | | | | | | Previously, this pass would look at the (static) set returned by getCallPreservedMask() and add those back as preserved in the case when isSafeForNoCSROpt() returns false. A problem is that a target may have to save some registers even when NoCSROpt takes place. For instance, on SystemZ, the return register is needed upon return from a function. Furthermore, getCallPreservedMask() only includes the registers that the target actually wishes to emit save/restore instructions for. This means that subregs and (fully saved) superregs are missing. This patch instead takes the (dynamic) set returned by target for the function from determineCalleeSaves() and then adds sub/super regs to build the set to be used when building the RegMask for the function. Review: Quentin Colombet, Ulrich Weigand https://reviews.llvm.org/D46315 llvm-svn: 333261
* [DebugInfo] Maintain DI when converting GEP to bitcastVedant Kumar2018-05-241-0/+1
| | | | | | | | | | | When a GEP with all zero indices is converted to bitcast, its DI wasn't copied over to the newly created instruction. This patch fixes that bug. Patch by Kareem Ergawy! Differential Revision: https://reviews.llvm.org/D47347 llvm-svn: 333235
* [ScheduleDAGInstrs / buildSchedGraph] Clear subregister entries also.Jonas Paulsson2018-05-241-7/+8
| | | | | | | | | | | | | | | In addPhysRegDeps, subregister entries of the defined register were previously not removed from Uses or Defs, which resulted in extra redundant edges for subregs around the register definition. This is principally NFC (in very rare cases some node got a different height). This makes the DAG more readable and efficient in some cases. Review: Andy Trick https://reviews.llvm.org/D46838 llvm-svn: 333165
* [DebugInfo] Maintain DI for sunken bitcastsVedant Kumar2018-05-231-0/+1
| | | | | | | | | | | | When a bitcast is being sunk in -codegenprepare pass, its DI wasn't copied over to the newly created instruction. This patch fixes that bug. Patch by Kareem Ergawy! Differential Revision: https://reviews.llvm.org/D47282 llvm-svn: 333133
* [GlobalISel] NFCI, Getting GlobalISel ~5% fasterRoman Tereshin2018-05-233-25/+20
| | | | | | | | | | | | by replacing DenseMap with IndexedMap for LLTs within MRI, as benchmarked by cross-compiling sqlite3 amalgamation for AArch64 on x86 machine. Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46809 llvm-svn: 333125
* [WebAssembly] Add functions for EHScopesHeejin Ahn2018-05-235-35/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There are functions using the term 'funclet' to refer to both 1. an EH scopes, the structure of BBs that starts with catchpad/cleanuppad and ends with catchret/cleanupret, and 2. a small function that gets outlined in AsmPrinter, which is the original meaning of 'funclet'. So far the two have been the same thing; EH scopes are always outlined in AsmPrinter as funclets at the end of the compilation pipeline. But now wasm also uses scope-based EH but does not outline those, so we now need to correctly distinguish those two use cases in functions. This patch splits `MachineBasicBlock::isFuncletEntry` into `isFuncletEntry` and `isEHScopeEntry`, and `MachineFunction::hasFunclets` into `hasFunclets` and `hasEHScopes`, in order to distinguish the two different use cases. And this also changes some uses of the term 'funclet' to 'scope' in `getFuncletMembership` and change the function name to `getEHScopeMembership` because this function is not about outlined funclets but about EH scope memberships. This change is in the same vein as D45559. Reviewers: majnemer, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D47005 llvm-svn: 333045
* [MachineOutliner] Add "thunk" outlining for AArch64.Eli Friedman2018-05-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | When we're outlining a sequence that ends in a call, we can save up to three instructions in the outlined function by turning the call into a tail-call. I refer to this as thunk outlining because the resulting outlined function looks like a thunk; suggestions welcome for a better name. In addition to making the outlined function shorter, thunk outlining allows outlining calls which would otherwise be illegal to outline: we don't need to save/restore LR, so we don't need to prove anything about the stack access patterns of the callee. To make this work effectively, I also added MachineOutlinerInstrType::LegalTerminator to the generic MachineOutliner code; this allows treating an arbitrary instruction as a terminator in the suffix tree. Differential Revision: https://reviews.llvm.org/D47173 llvm-svn: 333015
* [DWARFv5] Put the DWO ID in its place.Paul Robinson2018-05-223-5/+24
| | | | | | | | | | | | In DWARF v5, the DWO ID is in the (split/skeleton) CU header, not an attribute on the CU DIE. This changes the size of those headers, so use the parsed size whenever we have one, for simplicitly. Differential Revision: https://reviews.llvm.org/D47158 llvm-svn: 333004
* [DAG] fold FP binops with undef operands to NaNSanjay Patel2018-05-211-11/+12
| | | | | | | | | | | | | | | | | | This is the FP sibling of D43141 with the corresponding IR change in rL327212. We can't propagate undef here because if a variable operand is a NaN, these binops must propagate NaN. Neither global nor node-level fast-math makes a difference. If we have 'nnan', I think later folds can turn the NaN into undef. The tests in X86/fp-undef.ll are meant to be the definitive verification for these folds - everything reduces identically now. The other test changes are collateral damage. They may need to be altered to preserve their intent. Differential Revision: https://reviews.llvm.org/D47026 llvm-svn: 332920
* [DAGCombiner] isAllOnesConstantOrAllOnesSplatConstant(): look through bitcastsRoman Lebedev2018-05-211-6/+9
| | | | | | | | | | | | Summary: As pointed out in D46528, we errneously transform cases like `xor X, -1`, even though we use said function. It's because the `-1` is actually a bitcast there. So i think we can just look through it in the function. Differential Revision: https://reviews.llvm.org/D47156 llvm-svn: 332905
* [DAGCombine][X86][AArch64] Masked merge unfolding: vector edition.Roman Lebedev2018-05-211-4/+0
| | | | | | | | | | | | | | | Summary: This **appears** to be the last missing piece for the masked merge pattern handling in the backend. This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]]. [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly. Previously, `andps`+`andnps` / `bsl` would be generated. (see `@out`) Now, they would no longer be generated (see `@in`), and we need to make sure that they are generated. Differential Revision: https://reviews.llvm.org/D46528 llvm-svn: 332904
* [DAGCombiner] Use computeKnownBits to match rotate patterns that have had ↵Craig Topper2018-05-211-7/+18
| | | | | | | | | | | | | | | | their amount masking modified by simplifyDemandedBits SimplifyDemandedBits can remove bits from the masks for the shift amounts we need to see to detect rotates. This patch uses zeroes from computeKnownBits to fill in some of these mask bits to make the match work. As currently written this calls computeKnownBits even when the mask hasn't been simplified because it made the code simpler. If we're worried about compile time performance we can improve this. I know we're talking about making a rotate intrinsic, but hopefully we can go ahead and do this change and just make sure the rotate intrinsic also handles it. Differential Revision: https://reviews.llvm.org/D47116 llvm-svn: 332895
* CodeGen: Add a dwo output file argument to addPassesToEmitFile and hook it ↵Peter Collingbourne2018-05-212-6/+11
| | | | | | | | | | up to dwo output. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47089 llvm-svn: 332881
* [GlobalMerge] Exit early if only one global is to be mergedHaicheng Wu2018-05-191-1/+9
| | | | | | | | To save some compilation time and prevent some unnecessary changes. Differential Revision: https://reviews.llvm.org/D46640 llvm-svn: 332813
* DAG: Fix crash on shift with large shift amountsMatt Arsenault2018-05-181-2/+2
| | | | | | Fixes bug 37521. llvm-svn: 332774
* MC: Change the streamer ctors to take an object writer instead of a stream. ↵Peter Collingbourne2018-05-181-3/+5
| | | | | | | | | | | | | | NFCI. The idea is that a client that wants split dwarf would create a specific kind of object writer that creates two files, and use it to create the streamer. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47050 llvm-svn: 332749
* Revert changes from D46265.Than McIntosh2018-05-181-5/+2
| | | | | | | | | | | | This is a revert of the changes from https://reviews.llvm.org/D46265; the new test introduced (test/CodeGen/X86/PR37310.mir) causes buildbot failures. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47061 llvm-svn: 332742
* StackColoring: better handling of statically unreachable codeThan McIntosh2018-05-181-2/+5
| | | | | | | | | | | | | | Summary: Avoid assert/crash during liveness calculation in situations where the incoming machine function has statically unreachable BBs. Fixes PR37130. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46265 llvm-svn: 332707
* Revert "Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for ↵Eric Christopher2018-05-181-7/+15
| | | | | | | | | | | | | | | debug info emission."" This reapplies commits: r330271, r330592, r330779. [DEBUG] Initial adaptation of NVPTX target for debug info emission. Summary: Patch adds initial emission of the debug info for NVPTX target. Currently, only .file and .loc directives are emitted, everything else is commented out to not break the compilation of Cuda. llvm-svn: 332689
* Tidy comment up a bit.Eric Christopher2018-05-181-1/+1
| | | | llvm-svn: 332687
* [MachineOutliner] Count savings from outlining in bytes.Eli Friedman2018-05-181-7/+12
| | | | | | | | | | Counting the number of instructions is both unintuitive and inaccurate. On AArch64, this only affects the generated remarks and certain rare pseudo-instructions, but it will have a bigger impact on other targets. Differential Revision: https://reviews.llvm.org/D46921 llvm-svn: 332685
* Resubmit [pdb] Change /DEBUG:GHASH to emit 8 byte hashes."Zachary Turner2018-05-171-2/+2
| | | | | | | This fixes the remaining failing tests, so resubmitting with no functional change. llvm-svn: 332676
* Revert "[pdb] Change /DEBUG:GHASH to emit 8 byte hashes."Zachary Turner2018-05-171-2/+2
| | | | | | | A few tests haven't been properly updated, so reverting while I have time to investigate proper fixes. llvm-svn: 332672
* [pdb] Change /DEBUG:GHASH to emit 8 byte hashes.Zachary Turner2018-05-171-2/+2
| | | | | | | | | | | | | | | | Previously we emitted 20-byte SHA1 hashes. This is overkill for identifying debug info records, and has the negative side effect of making object files bigger and links slower. By using only the last 8 bytes of a SHA1, we get smaller object files and ~10% faster links. This modifies the format of the .debug$H section by adding a new value for the hash algorithm field, so that the linker will still work when its object files have an old format. Differential Revision: https://reviews.llvm.org/D46855 llvm-svn: 332669
* [WebAssembly] Add Wasm personality and isScopedEHPersonality()Heejin Ahn2018-05-173-6/+6
| | | | | | | | | | | | | | | | | | | | | Summary: - Add wasm personality function - Re-categorize the existing `isFuncletEHPersonality()` function into two different functions: `isFuncletEHPersonality()` and `isScopedEHPersonality(). This becomes necessary as wasm EH uses scoped EH instructions (catchswitch, catchpad/ret, and cleanuppad/ret) but not outlined funclets. - Changed some callsites of `isFuncletEHPersonality()` to `isScopedEHPersonality()` if they are related to scoped EH IR-level stuff. Reviewers: majnemer, dschuff, rnk Subscribers: jfb, sbc100, jgravelle-google, eraman, JDevlieghere, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D45559 llvm-svn: 332667
* [CodeGen] Use MachineInstr::getOperand(0) instead of gets the defs ↵Craig Topper2018-05-161-1/+1
| | | | | | | | iterator_range and calling begin. NFC Defs are well defined to come first in MachineInstr operand list. No need for a more complex indirection. llvm-svn: 332559
* [STLExtras] Add size() for ranges, and remove distance()Vedant Kumar2018-05-161-1/+1
| | | | | | | | | | r332057 introduced distance() for ranges. Based on post-commit feedback, this renames distance() to size(). The new size() is also only enabled when the operation is O(1). Differential Revision: https://reviews.llvm.org/D46976 llvm-svn: 332551
* Fix small grammar-o.Eric Christopher2018-05-161-1/+1
| | | | llvm-svn: 332522
* [DAG] Prune cycle check in store merge.Nirav Dave2018-05-161-18/+54
| | | | | | | | | | | | | | | | | | | | As part of merging stores we check that fusing the nodes does not cause a cycle due to one candidate store being indirectly dependent on another store (this may happen via chained memory copies). This is done by searching if a store is a predecessor to another store's value. Prune the search at the candidate search's root node which is a predecessor to all candidate stores. This reduces the size of the subgraph searched in large basic blocks. Reviewers: jyknight Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D46955 llvm-svn: 332490
* [DAG] Defer merge store cycle checking to just before merge. NFCI.Nirav Dave2018-05-161-8/+20
| | | | llvm-svn: 332489
* [AArch64] Gangup loads and stores for pairing.Sirish Pande2018-05-162-4/+86
| | | | | | | | | | Keep loads and stores together (target defines how many loads and stores to gang up), such that it will help in pairing and vectorization. Differential Revision https://reviews.llvm.org/D46477 llvm-svn: 332482
* [GlobalISel][IRTranslator] Split aggregates during IR translation.Amara Emerson2018-05-161-135/+280
| | | | | | | | | | | | | | | | | | | | | We currently handle all aggregates by creating one large LLT, and letting the legalizer deal with splitting them up. However using this approach means that we can't support big endian code correctly. This patch changes the way that the IRTranslator deals with aggregate values, by splitting them up into their constituent element values. To do this, parts of the translator need to be modified to deal with multiple VRegs for a single Value. A new Value to VReg mapper is introduced to help keep compile time under control, currently there is no measurable impact on CTMark despite the extra code being generated in some cases. Patch is based on the original work of Tim Northover. Differential Revision: https://reviews.llvm.org/D46018 llvm-svn: 332449
* Emit a left-shift instead of a power-of-two multiply for jump-tablesAlexander Richardson2018-05-161-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: SelectionDAGLegalize::ExpandNode() inserts an ISD::MUL when lowering a BR_JT opcode. While many backends optimize this multiply into a shift, e.g. the MIPS backend currently always lowers this into a sequence of load-immediate+multiply+mflo in MipsSETargetLowering::lowerMulDiv(). I initially changed the multiply to a shift in the MIPS backend but it turns out that would not have handled the MIPSR6 case and was a lot more code than doing it in LegalizeDAG. I believe performing this simple optimization in LegalizeDAG instead of each individual backend is the better solution since this also fixes other backeds such as MSP430 which calls the multiply runtime function __mspabi_mpyi without this patch. Reviewers: sdardis, atanasyan, pftbest, asl Reviewed By: sdardis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45760 llvm-svn: 332439
* [DebugInfo] Only handle DBG_VALUE in InlineSpiller.Shiva Chen2018-05-161-2/+8
| | | | | | | | | | | | | The instructions using registers should be DBG_VALUE and normal instructions. Use isDebugValue() to filter out DBG_VALUE and add an assert to ensure there is no other kind of debug instructions using the registers. Differential Revision: https://reviews.llvm.org/D46739 Patch by Hsiangkai Wang. llvm-svn: 332427
* [MachineOutliner] Add optsize markings to outlined functions.Eli Friedman2018-05-151-0/+8
| | | | | | | | | It doesn't matter much this late in the pipeline, but one place that does check for it is the function alignment code. Differential Revision: https://reviews.llvm.org/D46373 llvm-svn: 332415
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