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* Fix r141744.Evan Cheng2011-10-121-1/+19
| | | | | | | | | 1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. llvm-svn: 141747
* Refine r141689 with a tri-state variable.Evan Cheng2011-10-111-19/+23
| | | | | | Also teach MachineLICM to avoid "speculation" when register pressure is high. llvm-svn: 141744
* Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher2011-10-112-3/+21
| | | | | | | | | | | | | file. Since it should only be used when necessary propagate it through the backend code generation and tweak testcases accordingly. This helps with code like in clang's test/CodeGen/debug-info-line.c where we have multiple #line directives within a single lexical block and want to generate only a single block that contains each file change. Part of rdar://10246360 llvm-svn: 141729
* Formatting.Eric Christopher2011-10-111-2/+1
| | | | llvm-svn: 141728
* N.B. This is with the new EH scheme:Bill Wendling2011-10-111-0/+5
| | | | | | | | | | | | | | | The blocks with invokes have branches to the dispatch block, because that more correctly models the behavior of the CFG. The dispatch of course has edges to the landing pads. Those landing pads could contain invokes, which then have branches back to the dispatch. This creates a loop. The machine LICM pass looks at this loop and thinks it can hoist elements out of it. But because the dispatch is an alternate entry point into the program, the hoisted instructions won't be executed. I wasn't able to get a testcase which was small and could reproduce all of the time. The function_try_block.cpp in llvm-test was where this showed up. llvm-svn: 141726
* Add dominance check for the instruction being hoisted.Devang Patel2011-10-111-1/+46
| | | | | | | For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. llvm-svn: 141689
* Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem2011-10-111-0/+25
| | | | llvm-svn: 141667
* Add support for legalization of vector trunc-store where the saved scalar ↵Nadav Rotem2011-10-111-13/+13
| | | | | | type is illegal (for example, v2i16 on systems where the smallest store size is i32) llvm-svn: 141661
* Cleanup the trunc-store legalization code and add asserts.Nadav Rotem2011-10-111-68/+87
| | | | llvm-svn: 141659
* Revert r141569 and r141576.Devang Patel2011-10-101-29/+0
| | | | llvm-svn: 141594
* Give targets a chance to expand even standard pseudos.Jakob Stoklund Olesen2011-10-101-4/+12
| | | | | | | | | | | Allow targets to expand COPY and other standard pseudo-instructions before they are expanded with copyPhysReg(). This allows the target to examine the COPY instruction for extra operands indicating it can be widened to a preferable super-register copy. See the ARM -widen-vmovs option. llvm-svn: 141578
* If loop header is also loop exiting block then it may not be safe to hoist ↵Devang Patel2011-10-101-5/+4
| | | | | | instructions. llvm-svn: 141576
* Add dominance check for the instruction being hoisted.Devang Patel2011-10-101-0/+30
| | | | | | | For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. llvm-svn: 141569
* Use the code that lowers the arguments and spills any values which are aliveBill Wendling2011-10-081-2/+125
| | | | | | | | across unwind edges. This is for the back-end which expects such things. The code is from the original SjLj EH pass. llvm-svn: 141463
* Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling2011-10-071-2/+8
| | | | | | do. This will be useful later on with the new SJLJ stuff. llvm-svn: 141416
* PostRA scheduler fix. Clear stale loop dependencies.Andrew Trick2011-10-072-1/+3
| | | | | | Fixes <rdar://problem/10235725> llvm-svn: 141357
* whitespaceAndrew Trick2011-10-072-3/+3
| | | | llvm-svn: 141356
* Remove the old atomic instrinsics. autoupgrade functionality is included ↵Eli Friedman2011-10-062-67/+0
| | | | | | with this patch. llvm-svn: 141333
* Modify the mapping from landing pad to call sites to accept more than one callBill Wendling2011-10-053-3/+6
| | | | | | site. llvm-svn: 141226
* Add an ivar that maps a landing pad's EH symbol to the call sites that may jumpBill Wendling2011-10-051-0/+8
| | | | | | | to the landing pad. This will be used by the back-end to generate the jump tables for dispatching the arriving longjmp in sjlj eh. llvm-svn: 141224
* Small refactoring. Cache the FunctionInfo->MBB into a local variable.Bill Wendling2011-10-051-7/+7
| | | | llvm-svn: 141221
* Fix sub-register operand verification.Jakob Stoklund Olesen2011-10-051-12/+25
| | | | | | | | | PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. llvm-svn: 141220
* Fix comment to reflect the new EH stuff.Bill Wendling2011-10-051-1/+1
| | | | llvm-svn: 141218
* Remove unused DstSubIdx argument.Jakob Stoklund Olesen2011-10-051-23/+5
| | | | llvm-svn: 141214
* Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen2011-10-052-27/+52
| | | | | | | | | | | | EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to constrain the %dst register class. RegisterCoalescer will apply the necessary constraints if it decides to eliminate the COPY. The %src register class does need to be constrained to something with the right sub-registers, though. This is currently done manually with COPY_TO_REGCLASS nodes. They can possibly be removed after this patch. llvm-svn: 141207
* Simplify INSERT_SUBREG emission.Jakob Stoklund Olesen2011-10-051-27/+19
| | | | | | | | | | | | | | The register class created by INSERT_SUBREG and SUBREG_TO_REG must be legal and support the SubIdx sub-registers. The new getSubClassWithSubReg() hook can compute that. This may create INSERT_SUBREG instructions defining a larger register class than the sub-register being inserted. That is OK, RegisterCoalescer will constrain the register class as needed when it eliminates the INSERT_SUBREG instructions. llvm-svn: 141198
* Add a FIXME.Jakob Stoklund Olesen2011-10-051-0/+4
| | | | | | | | TwoAddressInstructionPass should annotate instructions with <undef> flags when it lower REG_SEQUENCE instructions. LiveIntervals should not be in the business of modifying code (except for kill flags, perhaps). llvm-svn: 141187
* Also add <imp-use,kill> flags for redefined super-registers.Jakob Stoklund Olesen2011-10-051-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 is rewritten as: %D2<def> = COPY %D0, %Q1<imp-def> %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def> The first COPY doesn't care about the previous value of %Q1, so it doesn't read that register. The second COPY is a partial redefinition of %Q1, so it implicitly kills and redefines that register. This makes it possible to recognize instructions that can harmlessly clobber the full super-register. The write and don't read the super-register. llvm-svn: 141139
* Also add <def,undef> flags when coalescing sub-registers.Jakob Stoklund Olesen2011-10-051-0/+8
| | | | | | | | RegisterCoalescer can create sub-register defs when it is joining a register with a sub-register. Add <undef> flags to these new sub-register defs where appropriate. llvm-svn: 141138
* Teach the MC to output code/data region marker labels in MachO and ELF ↵Owen Anderson2011-10-041-1/+12
| | | | | | modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. llvm-svn: 141135
* Create a mapping between the landing pad basic block and the call site index ↵Bill Wendling2011-10-042-0/+5
| | | | | | for later use. llvm-svn: 141125
* Allow <undef> flags on def operands as well as uses.Jakob Stoklund Olesen2011-10-041-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The <undef> flag says that a MachineOperand doesn't read its register, or doesn't depend on the previous value of its register. A full register def never depends on the previous register value. A partial register def may depend on the previous value if it is intended to update part of a register. For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 The first copy instruction defines the full %vreg10 register with the bits not covered by dsub_0 defined as <undef>. It is not considered a read of %vreg10. The second copy modifies part of %vreg10 while preserving the rest. It has an implicit read of %vreg10. This patch adds a MachineOperand::readsReg() method to determine if an operand reads its register. Previously, this was modelled by adding a full-register <imp-def> operand to the instruction. This approach makes it possible to determine directly from a MachineOperand if it reads its register. No scanning of MI operands is required. llvm-svn: 141124
* Generic cleanup.Bill Wendling2011-10-041-23/+16
| | | | llvm-svn: 141050
* Don't carry over the dispatchsetup hack from the old system.Bill Wendling2011-10-031-7/+1
| | | | llvm-svn: 141040
* Move the grabbing of the jump buffer into the caller function, eliminating ↵Bill Wendling2011-10-031-31/+33
| | | | | | the need for returning a std::pair. llvm-svn: 141026
* Whitespace.Eric Christopher2011-10-031-1/+1
| | | | llvm-svn: 141005
* Typo.Eric Christopher2011-10-031-1/+1
| | | | llvm-svn: 141004
* Moved type construction out of the loop and added an assert on the legality ↵Nadav Rotem2011-10-011-10/+10
| | | | | | of the type. Formatted lines to the 80 char limit. llvm-svn: 140952
* When inferring the pointer alignment, if the global doesn't have an initializerBill Wendling2011-09-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | and the alignment is 0 (i.e., it's defined globally in one file and declared in another file) it could get an alignment which is larger than the ABI allows for that type, resulting in aligned moves being used for unaligned loads. For instance, in file A.c: struct S s; In file B.c: struct { // something long }; extern S s; void foo() { struct S p = s; // ... } this copy is a 'memcpy' which is turned into a series of 'movaps' instructions on X86. But this is wrong, because 'struct S' has alignment of 4, not 16. llvm-svn: 140902
* Promote comment to doxycomment. Adjust whitespace. No functionality change.Nick Lewycky2011-09-301-4/+3
| | | | llvm-svn: 140899
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-304-9/+10
| | | | | | It will soon need the context. llvm-svn: 140896
* Comment grammar fixes.Torok Edwin2011-09-301-5/+6
| | | | | | thanks to Duncan. llvm-svn: 140850
* Instead of crashing when MCAsmInfo is NULL, add an assert.Torok Edwin2011-09-301-0/+5
| | | | | | | This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location, and if you include the old one by accident you will trigger this assert. llvm-svn: 140848
* Clean up uses of switch instructions so they are not dependent on the ↵Eli Friedman2011-09-291-2/+2
| | | | | | operand ordering. Patch by Stepan Dyatkovskiy. llvm-svn: 140803
* Place this bracket according to the LLVM style.Duncan Sands2011-09-291-2/+1
| | | | llvm-svn: 140784
* Remove NumImplicitOps which is now unused.Jakob Stoklund Olesen2011-09-291-18/+12
| | | | llvm-svn: 140767
* Use the local we already set up.Eric Christopher2011-09-291-1/+1
| | | | llvm-svn: 140745
* Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.Jakob Stoklund Olesen2011-09-291-81/+53
| | | | | | | | | | | | | | | | | | | | | | | The function needs to scan the implicit operands anyway, so no performance is won by caching the number of implicit operands added to an instruction. This also fixes a bug when adding operands after an implicit operand has been added manually. The NumImplicitOps count wasn't kept up to date. MachineInstr::addOperand() will now consistently place all explicit operands before all the implicit operands, regardless of the order they are added. It is possible to change an MI opcode and add additional explicit operands. They will be inserted before any existing implicit operands. The only exception is inline asm instructions where operands are never reordered. This is because of a hack that marks explicit clobber regs on inline asm as <implicit-def> to please the fast register allocator. This hack can go away when InstrEmitter and FastIsel can add exact <dead> flags to physreg defs. llvm-svn: 140744
* Have the SjLjEHPrepare pass do some more heavy lifting.Bill Wendling2011-09-281-34/+55
| | | | | | | | Upon further review, most of the EH code should remain written at the IR level. The part which breaks SSA form is the dispatch table, so that part will be moved to the back-end. llvm-svn: 140730
* A typeid of zero means a cleanup, not a catch. This case occursDuncan Sands2011-09-281-2/+4
| | | | | | when there is both a catch and a cleanup. Correct the comment. llvm-svn: 140686
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