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* Fix DW_AT_data_member_location for bit-fields. It points to the location of ↵Devang Patel2009-11-041-5/+12
| | | | | | annonymous field that covers respective field. llvm-svn: 86054
* Handle empty/tombstone keys for LiveIndex more cleanly. Check for index ↵Lang Hames2009-11-041-2/+2
| | | | | | sanity when constructing index list entries. llvm-svn: 86049
* Add some options to disable various code gen optimizations.Eric Christopher2009-11-041-8/+26
| | | | llvm-svn: 86044
* Array element size does not match array size but array is not a bitfield. Devang Patel2009-11-041-1/+3
| | | | llvm-svn: 86043
* Print out an informative comment for KILL instructions.Jakob Stoklund Olesen2009-11-041-0/+11
| | | | | | | | The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output. With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF. llvm-svn: 86041
* RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg,Evan Cheng2009-11-041-6/+22
| | | | | | | | and extract_subreg as a "copy" that defines a valno. Also fixes a typo. These two issues prevent a simple subreg coalescing from happening before. llvm-svn: 86022
* Fix CMake makefilesDouglas Gregor2009-11-041-0/+2
| | | | llvm-svn: 85994
* The Indexes Patch.Lang Hames2009-11-0315-965/+919
| | | | | | | | | | | | | | | | This introduces a new pass, SlotIndexes, which is responsible for numbering instructions for register allocation (and other clients). SlotIndexes numbering is designed to match the existing scheme, so this patch should not cause any changes in the generated code. For consistency, and to avoid naming confusion, LiveIndex has been renamed SlotIndex. The processImplicitDefs method of the LiveIntervals analysis has been moved into its own pass so that it can be run prior to SlotIndexes. This was necessary to match the existing numbering scheme. llvm-svn: 85979
* Fix branch folding bug for indirect branches: for a block containing onlyBob Wilson2009-11-031-1/+2
| | | | | | | | | | | | | | | an unconditional branch (possibly from tail merging), this code is trying to redirect all of its predecessors to go directly to the branch target, but that isn't feasible for indirect branches. The other predecessors (that don't end with indirect branches) could theoretically still be handled, but that is not easily done right now. The AnalyzeBranch interface doesn't currently let us distinguish jump table branches from indirect branches, and this code is currently handling jump tables. To avoid punting on address-taken blocks, we would have to give up handling jump tables. That seems like a bad tradeoff. llvm-svn: 85975
* Re-apply 85799. It turns out my code isn't buggy.Evan Cheng2009-11-031-17/+46
| | | | llvm-svn: 85947
* Do a scheduling pass ignoring anti-dependencies to identify candidate ↵David Goodwin2009-11-039-61/+179
| | | | | | registers that should be renamed. llvm-svn: 85939
* <rdar://problem/7352605>. When building schedule graph use mayAlias ↵David Goodwin2009-11-031-15/+43
| | | | | | information to avoid chaining loads/stores of spill slots with non-aliased memory ops. llvm-svn: 85934
* Ignore unnamed variables.Devang Patel2009-11-031-1/+3
| | | | llvm-svn: 85909
* Fix a funky "declared with greater visibility than the type of its field"Jeffrey Yasskin2009-11-031-2/+2
| | | | | | warning from gcc by removing VISIBILITY_HIDDEN attributes. llvm-svn: 85873
* Revert 85799 for now. It might be breaking llvm-gcc driver.Evan Cheng2009-11-021-46/+17
| | | | llvm-svn: 85827
* Chain dependencies used to enforce memory order should have latency of 0 ↵David Goodwin2009-11-021-14/+23
| | | | | | (except for true dependency of Store followed by aliased Load... we estimate that case with a single cycle of latency assuming the hardware will bypass) llvm-svn: 85807
* Initilize the machine LICM CSE map upon the first time an instruction is ↵Evan Cheng2009-11-021-17/+46
| | | | | | | | | | hoisted to the loop preheader. Add instructions which are already in the preheader block that may be common expressions of those that are hoisted out. These does get a few more instructions CSE'ed. llvm-svn: 85799
* Add PseudoSourceValue::mayAlias. It returns true if the object can ever ↵Evan Cheng2009-11-011-0/+17
| | | | | | alias any LLVM IR value. llvm-svn: 85762
* Fix a missing newline in the dwarf output code.Dan Gohman2009-10-311-0/+1
| | | | llvm-svn: 85684
* Make -print-machineinstrs more readable.Dan Gohman2009-10-316-66/+97
| | | | | | | | | | | | | | - Be consistent when referring to MachineBasicBlocks: BB#0. - Be consistent when referring to virtual registers: %reg1024. - Be consistent when referring to unknown physical registers: %physreg10. - Be consistent when referring to known physical registers: %RAX - Be consistent when referring to register 0: %reg0 - Be consistent when printing alignments: align=16 - Print jump table contents. - Don't print host addresses, in general. - and various other cleanups. llvm-svn: 85682
* Factor out more code into addCommonCodeGenPasses. The JIT wasn'tDan Gohman2009-10-311-32/+30
| | | | | | | | previously running CodePlacementOpt. Also print headers before each dump in -print-machineinstrs mode, so that it's clear which dump is which. llvm-svn: 85681
* Remove CodeGenLICM. It's largely obsoleted by MachineLICM's new abilityDan Gohman2009-10-311-6/+1
| | | | | | to unfold loop-invariant loads. llvm-svn: 85657
* When discarding SrcValue information, discard all of it so that codeDan Gohman2009-10-311-7/+5
| | | | | | that uses this information knows to behave conservatively. llvm-svn: 85654
* Fix 80-column violation.Dan Gohman2009-10-311-1/+2
| | | | llvm-svn: 85653
* Fix warning with gcc-4.0 and signed/unsigned.Eric Christopher2009-10-311-1/+1
| | | | llvm-svn: 85648
* Add assertion checks here to turn silent miscompiles into aborts.Dan Gohman2009-10-301-4/+8
| | | | llvm-svn: 85639
* Don't mark registers dead here when processing nodes with MVT::FlagDan Gohman2009-10-301-1/+5
| | | | | | | results. This works around a problem affecting targets which rely on MVT::Flag to handle physical register defs. llvm-svn: 85638
* Fix MachineLICM to use the correct virtual register class whenDan Gohman2009-10-301-2/+4
| | | | | | | | | | unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the opcode of the original operation without the load, not the load itself, MachineLICM needs to know the operand index in order to get the correct register class. Extend getOpcodeAfterMemoryUnfold to return this information. llvm-svn: 85622
* Stop the iterator in ValueLiveAt from potentially running off the end of the ↵Lang Hames2009-10-302-4/+7
| | | | | | interval. llvm-svn: 85599
* Don't delete blocks which have their address taken.Dan Gohman2009-10-301-2/+3
| | | | llvm-svn: 85572
* Mention if a block has its address taken in debug output.Dan Gohman2009-10-301-0/+1
| | | | llvm-svn: 85571
* Add support for BlockAddress static initializers.Dan Gohman2009-10-301-0/+2
| | | | llvm-svn: 85562
* Add a FIXME comment.Dan Gohman2009-10-301-0/+2
| | | | llvm-svn: 85559
* Add some comments.Dan Gohman2009-10-301-0/+8
| | | | llvm-svn: 85558
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-307-3/+83
| | | | llvm-svn: 85556
* Between scheduling regions, correctly maintain anti-dep breaking state so ↵David Goodwin2009-10-291-5/+7
| | | | | | that we don't incorrectly rename registers that span these regions. llvm-svn: 85537
* Remove some unnecessary spaces in debug output.Dan Gohman2009-10-291-3/+3
| | | | llvm-svn: 85536
* Move some code from being emitted as boilerplate duplicated in everyDan Gohman2009-10-291-0/+52
| | | | | | *ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp. llvm-svn: 85530
* Fix a couple of bugs in aggressive anti-dep breaking.David Goodwin2009-10-292-36/+62
| | | | llvm-svn: 85522
* Refactor complicated predicate into a separate function.Bob Wilson2009-10-291-17/+33
| | | | llvm-svn: 85519
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-292-4/+8
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Refactor the code for unfolding a load into a separate function.Dan Gohman2009-10-291-50/+62
| | | | llvm-svn: 85515
* Reapply r85338.Bill Wendling2009-10-292-2/+22
| | | | llvm-svn: 85514
* When the function is doing dynamic stack realignment, the spill slot will beJim Grosbach2009-10-291-2/+2
| | | | | | | | indexed via the stack pointer, even if a frame pointer is present. Update the heuristic to place it nearest the stack pointer in that case, rather than nearest the frame pointer. llvm-svn: 85474
* When there is a 2-instruction spill sequence, recordDale Johannesen2009-10-291-2/+3
| | | | | | | | the second (store) instruction in SpillSlotToUsesMap consistently. I don't think this matters functionally, but it's cleaner and Evan wants it this way. llvm-svn: 85463
* Don't put in these EH changes.Bill Wendling2009-10-292-293/+37
| | | | llvm-svn: 85460
* Reverting r85338 for now. It's causing a bootstrap failure on PPC darwin9.Bill Wendling2009-10-294-59/+295
| | | | | | | | --- Reverse-merging r85338 into '.': U lib/CodeGen/SimpleRegisterCoalescing.cpp U lib/CodeGen/SimpleRegisterCoalescing.h llvm-svn: 85454
* Reimplement BranchFolding change to avoid tail merging for a 1 instructionBob Wilson2009-10-281-13/+15
| | | | | | | common tail, except when the OptimizeForSize function attribute is present. Radar 7338114. llvm-svn: 85441
* When we generate spill code, then decide we don't needDale Johannesen2009-10-281-1/+4
| | | | | | | | | | to spill after all, we weren't handling 2-instruction spill sequences correctly (PPC Altivec). We need to remove the store in this case. Removing the other instruction(s) would be goodness but is not needed for correctness, and isn't done here. 7331562. llvm-svn: 85437
* Make sure we return the right sized type here.Eric Christopher2009-10-281-2/+5
| | | | llvm-svn: 85436
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