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authorDale Johannesen <dalej@apple.com>2009-10-28 21:56:18 +0000
committerDale Johannesen <dalej@apple.com>2009-10-28 21:56:18 +0000
commit14f162d9dcb0cf4ced08834eb27dc999982d1077 (patch)
tree264264d69ef027fd7acb694e91d79c3c9c777147 /llvm/lib/CodeGen
parent1fd4c577d2b8bfd32fa80f0a635d448c9cad5213 (diff)
downloadbcm5719-llvm-14f162d9dcb0cf4ced08834eb27dc999982d1077.tar.gz
bcm5719-llvm-14f162d9dcb0cf4ced08834eb27dc999982d1077.zip
When we generate spill code, then decide we don't need
to spill after all, we weren't handling 2-instruction spill sequences correctly (PPC Altivec). We need to remove the store in this case. Removing the other instruction(s) would be goodness but is not needed for correctness, and isn't done here. 7331562. llvm-svn: 85437
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/VirtRegRewriter.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/VirtRegRewriter.cpp b/llvm/lib/CodeGen/VirtRegRewriter.cpp
index 107c19ad019..a9ff1ad9aed 100644
--- a/llvm/lib/CodeGen/VirtRegRewriter.cpp
+++ b/llvm/lib/CodeGen/VirtRegRewriter.cpp
@@ -1430,6 +1430,7 @@ private:
std::vector<MachineOperand*> &KillOps,
VirtRegMap &VRM) {
+ MachineBasicBlock::iterator oldNextMII = next(MII);
TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
MachineInstr *StoreMI = next(MII);
VRM.addSpillSlotUse(StackSlot, StoreMI);
@@ -1466,7 +1467,9 @@ private:
}
}
- LastStore = next(MII);
+ // Allow for multi-instruction spill sequences, as on PPC Altivec. Presume
+ // the last of multiple instructions is the actual store.
+ LastStore = prior(oldNextMII);
// If the stack slot value was previously available in some other
// register, change it now. Otherwise, make the register available,
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