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* Add some comments.Dan Gohman2010-06-241-0/+7
| | | | llvm-svn: 106809
* Teach EmitLiveInCopies to omit copies for unused virtual registers,Dan Gohman2010-06-241-14/+25
| | | | | | and to clean up unused incoming physregs from the live-in list. llvm-svn: 106805
* It's possible that a flag is added to the SDNode that points back to theBill Wendling2010-06-241-11/+19
| | | | | | | original SDNode. This is badness. Also, this function allows one SDNode to point multiple flags to another SDNode. Badness as well. llvm-svn: 106793
* DBG_VALUE machine instruction pointing to undefined register for a variable ↵Devang Patel2010-06-241-4/+1
| | | | | | | | justify a separate scope if the variable is inlined function's argument. Radar 8122864. llvm-svn: 106792
* Don't return a std::vector in the Spiller interface, but take a reference to aJakob Stoklund Olesen2010-06-243-33/+38
| | | | | | | | vector instead. This avoids needless copying and allocation. Add documentation. llvm-svn: 106788
* Remove the now unused LiveIntervals::getVNInfoSourceReg().Jakob Stoklund Olesen2010-06-241-31/+0
| | | | | | | This method was always a bit too simplistic for the real world. It didn't really deal with subregisters and such. llvm-svn: 106781
* Teach AdjustCopiesBackFrom to also use CoalescerPair to identify compatible ↵Jakob Stoklund Olesen2010-06-242-16/+13
| | | | | | copies. llvm-svn: 106780
* Remove the -fast-spill option.Jakob Stoklund Olesen2010-06-241-87/+0
| | | | | | | This code path has never really been used, and we are going to be handling spilling through the Spiller interface in the future. llvm-svn: 106777
* Loosen up the requirements in the Horrible Hack(tm) to include all selectorsBill Wendling2010-06-241-30/+10
| | | | | | | | which don't have a catch-all associated with them not just clean-ups. This fixes the SingleSource/Benchmarks/Shootout-C++/except.cpp testcase that broke because of my change r105902. llvm-svn: 106772
* Replace a big gob of old coalescer logic with the new CoalescerPair class.Jakob Stoklund Olesen2010-06-243-731/+219
| | | | | | | | | | CoalescerPair can determine if a copy can be coalesced, and which register gets merged away. The old logic in SimpleRegisterCoalescing had evolved into something a bit too convoluted. This second attempt fixes some crashes that only occurred Linux. llvm-svn: 106769
* Print the LSBs of a SlotIndex symbolically using letters referring to theJakob Stoklund Olesen2010-06-241-1/+3
| | | | | | | | | [L]oad, [u]se, [d]ef, or [S]tore slots. This makes it easier to see if two indices refer to the same instruction, avoiding mental mod 4 calculations. llvm-svn: 106766
* Simplify this code; switch lowering shouldn't produce casesDan Gohman2010-06-241-12/+4
| | | | | | which trivially fold away. llvm-svn: 106765
* Be more strict about subreg-to-subreg copies in CoalescerPair.Jakob Stoklund Olesen2010-06-241-5/+15
| | | | | | Also keep track of the original DstREg before subregister adjustments. llvm-svn: 106753
* Verify that VNI kills are pointing to existing instructions.Jakob Stoklund Olesen2010-06-241-0/+1
| | | | | | | In this case it is essential that the kill is real because the spiller will decide to omit a spill if it thinks there is a later kill. llvm-svn: 106751
* Eliminate the other half of the BRCOND optimization, and updateDan Gohman2010-06-241-7/+0
| | | | | | as many tests as possible. llvm-svn: 106749
* Eliminate the first have of the optimization which eliminates BRCONDDan Gohman2010-06-241-3/+1
| | | | | | | | | | | | | when the condition is constant. This optimization shouldn't be necessary, because codegen shouldn't be able to find dead control paths that the IR-level optimizer can't find. And it's undesirable, because it encourages bugpoint to leave "br i1 false" branches in its output. And it wasn't updating the CFG. I updated all the tests I could, but some tests are too reduced and I wasn't able to meaningfully preserve them. llvm-svn: 106748
* Reapply r106634, now that the bug it exposed is fixed.Dan Gohman2010-06-244-111/+50
| | | | llvm-svn: 106746
* Optimize the "bit test" code path for switch lowering in theDan Gohman2010-06-241-15/+27
| | | | | | case where the bit mask has exactly one bit. llvm-svn: 106716
* Revert "Replace a big gob of old coalescer logic with the new CoalescerPair ↵Jakob Stoklund Olesen2010-06-244-205/+544
| | | | | | | | class." Whiny buildbots. llvm-svn: 106710
* Replace a big gob of old coalescer logic with the new CoalescerPair class.Jakob Stoklund Olesen2010-06-244-544/+205
| | | | | | | | CoalescerPair can determine if a copy can be coalesced, and which register gets merged away. The old logic in SimpleRegisterCoalescing had evolved into something a bit too convoluted. llvm-svn: 106701
* MorphNodeTo doesn't preserve the memory operands. Because we're morphing a nodeBill Wendling2010-06-231-0/+21
| | | | | | | into the same node, but with different non-memory operands, we need to replace the memory operands after it's finished morphing. llvm-svn: 106643
* Revert r106263, "Fold the ShrinkDemandedOps pass into the regular ↵Daniel Dunbar2010-06-234-50/+111
| | | | | | DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. llvm-svn: 106634
* Some targets don't require the fencing MEMBARRIER instructions surroundingJim Grosbach2010-06-232-0/+56
| | | | | | | | atomic intrinsics, either because the use locking instructions for the atomics, or because they perform the locking directly. Add support in the DAG combiner to fold away the fences. llvm-svn: 106630
* Add a few VNInfo data structure checks.Jakob Stoklund Olesen2010-06-231-2/+5
| | | | llvm-svn: 106627
* Revert r106066, "Create a more targeted fix for not sinking instructions ↵Daniel Dunbar2010-06-231-14/+53
| | | | | | | | | | into a range where it"... it causes bzip2 to be miscompiled by Clang. Conflicts: lib/CodeGen/MachineSink.cpp llvm-svn: 106614
* Also convert SUBREG_TO_REG to a KILL when relevant, like the other subregJakob Stoklund Olesen2010-06-221-7/+12
| | | | | | | | | instructions. This does not affect codegen much because SUBREG_TO_REG is only used by X86 and X86 does not use the register scavenger, but it prevents verifier errors. llvm-svn: 106583
* Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks outDan Gohman2010-06-223-75/+130
| | | | | | | into a utility routine, teach it how to update MachineLoopInfo, and make use of it in MachineLICM to split critical edges on demand. llvm-svn: 106555
* Remove the SimpleJoin optimization from SimpleRegisterCoalescing.Jakob Stoklund Olesen2010-06-222-512/+68
| | | | | | | | | Measurements show that it does not speed up coalescing, so there is no reason the keep the added complexity around. Also clean out some unused methods and static functions. llvm-svn: 106548
* Use pre-increment instead of post-increment when the result is not used.Dan Gohman2010-06-222-14/+14
| | | | llvm-svn: 106542
* When unfolding a load, avoid assuming which instruction thatDan Gohman2010-06-221-4/+18
| | | | | | kill and dead flags will end up on. llvm-svn: 106520
* Use single interface, using twine, to get named metadata.Devang Patel2010-06-221-2/+2
| | | | | | getNamedMetadata(). llvm-svn: 106518
* Tail merging pass shall not break up IT blocks. rdar://8115404Evan Cheng2010-06-223-7/+23
| | | | llvm-svn: 106517
* Discard special LLVM prefix from linkage name.Devang Patel2010-06-221-1/+2
| | | | llvm-svn: 106516
* Do not rely on Twine temporaries to survive.Devang Patel2010-06-221-3/+4
| | | | llvm-svn: 106515
* Fix the new load-unfolding code to update LiveVariable's dead flags,Dan Gohman2010-06-221-2/+8
| | | | | | in addition to the kill flags. llvm-svn: 106512
* Teach two-address lowering how to unfold a load to open up commutingDan Gohman2010-06-211-0/+84
| | | | | | | | | | | | | | | | | | | opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. llvm-svn: 106493
* Use A.append(...) instead of A.insert(A.end(), ...) when A is aDan Gohman2010-06-213-5/+5
| | | | | | SmallVector, and other SmallVector simplifications. llvm-svn: 106452
* Revert r106422, which is breaking the non-fast-isel path.Dan Gohman2010-06-212-51/+11
| | | | llvm-svn: 106423
* More changes for non-top-down fast-isel.Dan Gohman2010-06-212-11/+51
| | | | | | | | | | Split the code for materializing a value out of SelectionDAGBuilder::getValue into a helper function, so that it can be used in other ways. Add a new getNonRegisterValue function which uses it, for use in code which doesn't want a CopyFromReg even when FuncMap.ValueMap already has an entry for it. llvm-svn: 106422
* Do one lookup instead of two.Dan Gohman2010-06-211-2/+3
| | | | llvm-svn: 106415
* Generalize this to look in the regular ValueMap in addition toDan Gohman2010-06-211-1/+1
| | | | | | | the LocalValueMap, to make it more flexible when fast-isel isn't proceding straight top-down. llvm-svn: 106414
* Tidy.Bob Wilson2010-06-191-5/+5
| | | | llvm-svn: 106383
* Teach regular and fast isel to set dead flags on unused implicit defsDan Gohman2010-06-183-0/+47
| | | | | | on calls and similar instructions. llvm-svn: 106353
* Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean upJakob Stoklund Olesen2010-06-181-2/+5
| | | | | | the inserted INSERT_SUBREGs after us. llvm-svn: 106345
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-185-41/+57
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)Jim Grosbach2010-06-182-0/+13
| | | | llvm-svn: 106342
* TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREGJakob Stoklund Olesen2010-06-181-1/+8
| | | | | | | | | instructions, but it doesn't really understand live ranges, so the first INSERT_SUBREG uses an implicitly defined register. Fix it in LiveVariableAnalysis by adding the <undef> flag. llvm-svn: 106333
* Fix an inverted condition.Evan Cheng2010-06-181-1/+1
| | | | llvm-svn: 106330
* Fix cross initialization compilation error.Evan Cheng2010-06-181-1/+2
| | | | llvm-svn: 106324
* Teach iff-converter to properly count # of dups. It was not skipping over ↵Evan Cheng2010-06-181-1/+27
| | | | | | dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384. llvm-svn: 106323
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