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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-06-24 16:19:28 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-06-24 16:19:28 +0000 |
| commit | 3b2b46a700e7cf3c572fc2e5fea843b0085f8208 (patch) | |
| tree | 97ba8e919e8b8ca6ac993acb68f96ff5b6893f75 /llvm/lib/CodeGen | |
| parent | 7ccec092521f8f3b6d48767ac7c751a17c464038 (diff) | |
| download | bcm5719-llvm-3b2b46a700e7cf3c572fc2e5fea843b0085f8208.tar.gz bcm5719-llvm-3b2b46a700e7cf3c572fc2e5fea843b0085f8208.zip | |
Be more strict about subreg-to-subreg copies in CoalescerPair.
Also keep track of the original DstREg before subregister adjustments.
llvm-svn: 106753
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/RegisterCoalescer.cpp | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index b18f0957b62..b943a271b6f 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -63,7 +63,7 @@ bool CoalescerPair::isMoveInstr(const MachineInstr *MI, bool CoalescerPair::setRegisters(const MachineInstr *MI) { srcReg_ = dstReg_ = subIdx_ = 0; newRC_ = 0; - flipped_ = false; + flipped_ = crossClass_ = false; unsigned Src, Dst, SrcSub, DstSub; if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub)) @@ -78,6 +78,7 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) { std::swap(SrcSub, DstSub); flipped_ = true; } + origDstReg_ = Dst; const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); @@ -100,11 +101,19 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) { } else { // Both registers are virtual. - // Identical sub to sub. - if (SrcSub == DstSub) + // Both registers have subreg indices. + if (SrcSub && DstSub) { + // For now we only handle the case of identical indices in commensurate + // registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg + // FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg. + if (SrcSub != DstSub) + return false; + const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); + const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); + if (!getCommonSubClass(DstRC, SrcRC)) + return false; SrcSub = DstSub = 0; - else if (SrcSub && DstSub) - return false; // FIXME: Qreg:ssub_3 + Dreg:ssub_1 => QReg:dsub_1 + Dreg. + } // There can be no SrcSub. if (SrcSub) { @@ -124,6 +133,7 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) { newRC_ = getCommonSubClass(DstRC, SrcRC); if (!newRC_) return false; + crossClass_ = newRC_ != DstRC || newRC_ != SrcRC; } // Check our invariants assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual"); |

