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* Revert "[DAGCombine] Move AND nodes to multiple load leaves"Benjamin Kramer2017-12-141-124/+0
| | | | | | This reverts commit r320679. Causes miscompiles. llvm-svn: 320698
* [CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug outputFrancis Visoiu Mistrih2017-12-142-5/+3
| | | | | | | | | Work towards the unification of MIR and debug output by printing `<mcsymbol sym>` instead of `<MCSym=sym>`. Only debug syntax is affected. llvm-svn: 320685
* [CodeGen] Move printing MO_Metadata operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-142-6/+2
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320684
* [CodeGen] Print live-out register lists as liveout(...) in both MIR and ↵Francis Visoiu Mistrih2017-12-142-18/+20
| | | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `liveout(...)` instead of `<regliveout>`. Only debug syntax is affected. llvm-svn: 320683
* [CodeGen] Print global addresses as @foo in both MIR and debug outputFrancis Visoiu Mistrih2017-12-142-70/+67
| | | | | | | | | | | | Work towards the unification of MIR and debug output by printing `@foo` instead of `<ga:@foo>`. Also print target flags in the MIR format since most of them are used on global address operands. Only debug syntax is affected. llvm-svn: 320682
* [CodeGen] Print external symbols as $symbol in both MIR and debug outputFrancis Visoiu Mistrih2017-12-142-17/+13
| | | | | | | | | Work towards the unification of MIR and debug output by printing `$symbol` instead of `<es:symbol>`. Only debug syntax is affected. llvm-svn: 320681
* [DAGCombine] Move AND nodes to multiple load leavesSam Parker2017-12-141-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | Recommitting rL319773, which was reverted due to a recursive issue causing timeouts. This happened because I failed to check whether the discovered loads could be narrowed further. In the case of a tree with one or more narrow loads, that could not be further narrowed, as well as a node that would need masking, an AND could be introduced which could then be visited and recombined again with the same load. This could again create the masking load, with would be combined again... We now check that the load can be narrowed so that this process stops. Original commit message: Search from AND nodes to find whether they can be propagated back to loads, so that the AND and load can be combined into a narrow load. We search through OR, XOR and other AND nodes and all bar one of the leaves are required to be loads or constants. The exception node then needs to be masked off meaning that the 'and' isn't removed, but the loads(s) are narrowed still. Differential Revision: https://reviews.llvm.org/D41177 llvm-svn: 320679
* [SelectionDAG][X86] Improve legalization of v32i1 CONCAT_VECTORS of v16i1 ↵Craig Topper2017-12-141-0/+15
| | | | | | | | | | for AVX512F. A v32i1 CONCAT_VECTORS of v16i1 uses promotion to v32i8 to legalize the v32i1. This results in a bunch of extract_vector_elts and a build_vector that ultimately gets scalarized. This patch checks to see if v16i8 is legal and inserts a any_extend to that so that we can concat v16i8 to v32i8 and avoid creating the extracts. llvm-svn: 320674
* [SelectionDAG] When legalizing the result type of CONCAT_VECTORS, take into ↵Craig Topper2017-12-141-3/+8
| | | | | | | | | | account whether the input type also needs to be promoted. If so go ahead and get the promoted input vector to extract from. Previously, we would create a bunch of any_extends of extract_vector_elts with illegal input type that needs to be promoted. The legalization of those extract_vector_elts would then potentially introduce a truncate. So now we have a bunch of any_extends of truncates. By legalizing both parts together we avoid creating these extra nodes. The test changes seem to be because we were previously combining the build_vector with the any_extend before the any_extend got combined with the truncate. llvm-svn: 320669
* MC/AsmPrinter: Reduce code duplication.Matthias Braun2017-12-141-22/+2
| | | | | | | | | | Factor out duplicated code emitting mach-o version-min specifiers. This should be NFC but happens to fix a bug where the code in MCMachoStreamer didn't take the version skew between darwin and macos versions into account. llvm-svn: 320666
* CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-132-3/+8
| | | | | | | | | | | | | | | | | Two issues were found about machine inst scheduler when compiling ProRender with -g for amdgcn target: GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it should not since DBG_VALUE is not mapped in LiveIntervals. when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion. This patch fixes that. Differential Revision: https://reviews.llvm.org/D41132 llvm-svn: 320650
* [CodeView] Teach clang to emit the .debug$H COFF section.Zachary Turner2017-12-132-9/+48
| | | | | | | | | | | | | | | Currently this is an LLVM extension to the COFF spec which is experimental and intended to speed up linking. For now it is behind a hidden cl::opt flag, but in the future we can move it to a "real" cc1 flag and have the driver pass it through whenever it is appropriate. The patch to actually make use of this section in lld will come in a followup. Differential Revision: https://reviews.llvm.org/D40917 llvm-svn: 320649
* Remove redundant includes from lib/CodeGen.Michael Zolotukhin2017-12-1332-56/+0
| | | | llvm-svn: 320619
* Ignore metainstructions during the shrink wrap analysisAdrian Prantl2017-12-131-0/+4
| | | | | | | | | | Shrink wrapping should ignore DBG_VALUEs referring to frame indices, since the presence of debug information must not affect code generation. Differential Revision: https://reviews.llvm.org/D41187 llvm-svn: 320606
* [DAG] Promote ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-12-131-1/+24
| | | | | | | | Add missing case that was not implemented yet. Differential Revision: https://reviews.llvm.org/D38942 llvm-svn: 320567
* [CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and ↵Francis Visoiu Mistrih2017-12-133-6/+9
| | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`. Only debug syntax is affected. llvm-svn: 320566
* [CodeGen] Print target index operands as target-index(target-specific) + 8 ↵Francis Visoiu Mistrih2017-12-132-28/+24
| | | | | | | | | | in both MIR and debug output Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`. Only debug syntax is affected. llvm-svn: 320565
* [CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and ↵Francis Visoiu Mistrih2017-12-132-9/+14
| | | | | | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of `<cp#0-8>`. Only debug syntax is affected. Differential Revision: https://reviews.llvm.org/D41116 llvm-svn: 320564
* Revert "[CGP] Enable select in complex addr mode"Serguei Katkov2017-12-131-1/+1
| | | | | | | | Causes: Assertion `ScaledReg == nullptr' failed. This actually a revert of rL320551. llvm-svn: 320553
* [CGP] Enable select in complex addr modeSerguei Katkov2017-12-131-1/+1
| | | | | | | | | | | Enable select instruction handling in complex addr modes. Reviewers: john.brawn, reames, aaboud Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40634 llvm-svn: 320551
* Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun2017-12-1328-29/+29
| | | | | | | | | | Headers/Implementation files should be named after the class they declare/define. Also eliminated an `#include "llvm/CodeGen/LiveIntervalAnalysis.h"` in favor of `class LiveIntarvals;` llvm-svn: 320546
* Remove unnecessary includes; NFCMatthias Braun2017-12-131-0/+2
| | | | llvm-svn: 320545
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-127-4/+56
| | | | | | | | | | | | | | | | | | Summary: Add isRenamable() predicate to MachineOperand. This predicate can be used by machine passes after register allocation to determine whether it is safe to rename a given register operand. Register operands that aren't marked as renamable may be required to be assigned their current register to satisfy constraints that are not captured by the machine IR (e.g. ABI or ISA constraints). Reviewers: qcolombet, MatzeB, hfinkel Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39400 llvm-svn: 320503
* [CodeGen] Improve the consistency of instruction fusion*Evandro Menezes2017-12-111-24/+55
| | | | | | | | | | | When either instruction in a fused pair has no other dependency, besides on the other instruction, make sure that other instructions do not get scheduled between them. Additionally, avoid fusing an instruction more than once along the same dependency chain. Differential revision: https://reviews.llvm.org/D36704 llvm-svn: 320420
* [GlobalISel] Disable GISel for big endian.Amara Emerson2017-12-111-0/+9
| | | | | | | | | | | | | This is due to PR26161 needing to be resolved before we can fix big endian bugs like PR35359. The work to split aggregates into smaller LLTs instead of using one large scalar will take some time, so in the mean time we'll fall back to SDAG. Some ARM BE tests xfailed for now as a result. Differential Revision: https://reviews.llvm.org/D40789 llvm-svn: 320388
* [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)Sanjay Patel2017-12-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | At first, I tried to thread the x86 needle and use a target hook (isVectorShiftByScalarCheap()) to disable the transform only for non-splat pow-of-2 constants, but not AVX2, but only some element types, but...it's difficult. Here we just avoid the loop with the x86 vector transform that conflicts with the general DAG combine and preserve all of the existing behavior AFAICT otherwise. Some tests that will probably fail if someone does try to restrict this in a more targeted way for x86-only may be found in: test/CodeGen/X86/combine-mul.ll test/CodeGen/X86/vector-mul.ll test/CodeGen/X86/widen_arith-5.ll This should prevent the infinite looping seen with: https://bugs.llvm.org/show_bug.cgi?id=35579 Differential Revision: https://reviews.llvm.org/D41040 llvm-svn: 320374
* [DAGCombiner] Add combined indexed load to the work listNemanja Ivanovic2017-12-111-0/+1
| | | | | | | | | | This commit is the first part of https://reviews.llvm.org/D40348. In order to allow target combines to be performed on newly combined indexed loads, add them back to the worklist. The remainder of the above patch will be committed in subsequent revisions and will use this. Test cases will be included with those follow-up commits. llvm-svn: 320365
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-12-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 - fixes PR34564 - fixes PR35103 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 320355
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-111-0/+19
| | | | | | | | | | | | | | | | Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
* [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.Craig Topper2017-12-111-0/+16
| | | | | | We should probably also fold (mulhs/u X, 1) for vectors, but that's harder. llvm-svn: 320344
* [DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFCCraig Topper2017-12-111-4/+3
| | | | llvm-svn: 320343
* Relax unaligned access assertion when type is byte alignedDylan McKay2017-12-092-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This relaxes an assertion inside SelectionDAGBuilder which is overly restrictive on targets which have no concept of alignment (such as AVR). In these architectures, all types are aligned to 8-bits. After this, LLVM will only assert that accesses are aligned on targets which actually require alignment. This patch follows from a discussion on llvm-dev a few months ago http://llvm.1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html Reviewers: bogner, nemanjai, joerg, efriedma Reviewed By: efriedma Subscribers: efriedma, cactus, llvm-commits Differential Revision: https://reviews.llvm.org/D39946 llvm-svn: 320243
* Hardware-assisted AddressSanitizer (llvm part).Evgeniy Stepanov2017-12-091-10/+11
| | | | | | | | | | | | | | | | | | | | | Summary: This is LLVM instrumentation for the new HWASan tool. It is basically a stripped down copy of ASan at this point, w/o stack or global support. Instrumenation adds a global constructor + runtime callbacks for every load and store. HWASan comes with its own IR attribute. A brief design document can be found in clang/docs/HardwareAssistedAddressSanitizerDesign.rst (submitted earlier). Reviewers: kcc, pcc, alekseyshl Subscribers: srhines, mehdi_amini, mgorny, javed.absar, eraman, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D40932 llvm-svn: 320217
* Fix out-of-order stepping behavior in programs with sunk instructions.Paul Robinson2017-12-091-1/+11
| | | | | | | | | | | | | | | | | | | MachineSink attempts to place instructions near the basic blocks where they are needed. Once an instruction has been sunk, its location relative to other instructions no longer is consistent with the original source code. In order to ensure correct stepping in the debugger, the debug location for sunk instructions is either merged with the insertion point or erased if the target successor block is empty. Originally submitted as r318679, revised to fix sanitizer failure and improve testing. Patch by Matthew Voss! Differential Revision: https://reviews.llvm.org/D39933 llvm-svn: 320216
* [CodeGen] Move printing MO_Immediate operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-083-9/+21
| | | | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. Add support for operand subreg index as an immediate to debug printing and use ::print in the MIRPrinter. Differential Review: https://reviews.llvm.org/D40965 llvm-svn: 320209
* Generalize llvm::replaceDbgDeclare and actually support the use-case thatAdrian Prantl2017-12-082-3/+6
| | | | | | is mentioned in the documentation (inserting a deref before the plus_uconst). llvm-svn: 320203
* [CodeGen] Move printing MO_MachineBasicBlock operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-081-4/+2
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320141
* [CodeGen] Move printing MO_CImmediate operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-082-5/+3
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320140
* [CodeGen] Fix index when printing tied machine operandsFrancis Visoiu Mistrih2017-12-071-3/+3
| | | | llvm-svn: 320061
* [DAGCombiner] eliminate shuffle of insert elementSanjay Patel2017-12-071-0/+81
| | | | | | | | | | | | | | | | | | | I noticed this pattern in D38316 / D38388. We failed to combine a shuffle that is either repeating a scalar insertion at the same position in a vector or translated to a different element index. Like the earlier patch, this could be an instcombine too, but since we opted to make this a DAG transform earlier, I've made this one a DAG patch too. We do not need any legality checking because the new insert is identical to the existing insert except that it may have a different constant insertion operand. The constant insertion test in test/CodeGen/X86/vector-shuffle-combining.ll was the motivation for D38756. Differential Revision: https://reviews.llvm.org/D40209 llvm-svn: 320050
* [CodeGen] Use more getMFIfAvailableFrancis Visoiu Mistrih2017-12-071-16/+8
| | | | llvm-svn: 320046
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-0723-267/+276
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g' llvm-svn: 320022
* [SelectionDAG] In SplitVecOp_EXTRACT_VECTOR_ELT, simplify the code that ↵Craig Topper2017-12-071-11/+2
| | | | | | | | makes the type byte addressable. We can just extend the original vector to vXi1 and trust that the legalization process will revisit it. llvm-svn: 320013
* [SelectionDAG] Use TLI.getVectorIdxTy to determine type for an ↵Craig Topper2017-12-071-1/+2
| | | | | | EXTRACT_VECTOR_ELT index instead of hardcoding MVT::i8. llvm-svn: 320012
* Skip DBG instr in OptimizePHIs when looking for dead PHI cyclesMikael Holmen2017-12-071-1/+1
| | | | | | | | | | | | | | | | | | | Summary: Changed use_instructions() to use_nodbg_instructions() when building an instruction set. We don't want the presence of debug info to affect the code we generate. Reviewers: dblaikie, Eugene.Zelenko, chandlerc, aprantl Reviewed By: aprantl Subscribers: aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D40882 llvm-svn: 320010
* [WebAssembly] section kind can be codeSam Clegg2017-12-071-1/+12
| | | | | | | | | | | | | Currently, when creating a named section, the Wasm frontend forces it to use `SectionKind::Data`, whereas in fact C++ does generate code sections with custom names. Patch by Nicholas Wilson Differential Revision: https://reviews.llvm.org/D40906 llvm-svn: 320002
* [MachineCombiner] Add up latencies of all instructions in new pattern.Florian Hahn2017-12-061-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When calculating the RootLatency, we add up all the latencies of the deleted instructions. But for NewRootLatency we only add the latency of the new root instructions, ignoring the latencies of the other instructions inserted. This leads the combiner to underestimate the cost of patterns which add multiple instructions. This patch fixes that by summing up the latencies of all new instructions. For NewRootNode, the more complex getLatency function is used. Note that we may be slightly more precise than just summing up all latencies. For example, consider a pattern like r1 = INS1 .. r2 = INS2 .. r3 = INS3 r1, r2 I think in some other places, the total latency of the pattern would be estimated as lat(INS3) + max(lat(INS1), lat(INS2)). If you consider that worth changing, I think it would be best to do in a follow-up patch. Reviewers: Gerolf, sebpop, spop, fhahn Reviewed By: fhahn Subscribers: evandro, llvm-commits Differential Revision: https://reviews.llvm.org/D40307 llvm-svn: 319951
* [ARM][AArch64][DAG] Reenable post-legalize store mergeNirav Dave2017-12-061-12/+19
| | | | | | | | | | | | | | | | | | | | Reenable post-legalize stores with constant merging computation and corresponding test case. * Properly truncate store merge constants * Disable merging of truncated stores floating points * Ensure merges of constant stores into a single vector are constructed from legal elements. Reviewers: eastig, efriedma Reviewed By: eastig Subscribers: spatel, rengolin, aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40701 llvm-svn: 319899
* [CodeGen] Fix formatting error from r319885Francis Visoiu Mistrih2017-12-061-1/+1
| | | | llvm-svn: 319886
* [CodeGen] Better handling of detached MachineOperandsFrancis Visoiu Mistrih2017-12-061-33/+39
| | | | | | | Basically use getMFIfAvailable to check if we can crawl up to the function. llvm-svn: 319885
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