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* Fix this to match change to InlineAsm class.Chris Lattner2007-04-281-3/+3
| | | | llvm-svn: 36524
* Fix incorrect legalization of EHSELECTOR. This fixesChris Lattner2007-04-271-6/+10
| | | | | | CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326 llvm-svn: 36510
* Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not ↵Evan Cheng2007-04-271-4/+25
| | | | | | available. llvm-svn: 36501
* improve EH global handling, patch by Duncan Sands.Chris Lattner2007-04-271-6/+10
| | | | llvm-svn: 36499
* enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrapChris Lattner2007-04-261-1/+0
| | | | | | successfully! woohoo... llvm-svn: 36496
* Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32Anton Korobeynikov2007-04-261-1/+1
| | | | llvm-svn: 36490
* Fix a typo in a comment.Dan Gohman2007-04-261-1/+1
| | | | llvm-svn: 36485
* Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.Evan Cheng2007-04-265-10/+11
| | | | llvm-svn: 36483
* Minor bug.Evan Cheng2007-04-261-2/+2
| | | | llvm-svn: 36473
* Be careful when to add implicit kill / dead operands. Don't add them during ↵Evan Cheng2007-04-261-9/+17
| | | | | | / post reg-allocation. llvm-svn: 36458
* Match MachineFunction::UsedPhysRegs changes.Evan Cheng2007-04-255-48/+25
| | | | llvm-svn: 36452
* Change UsedPhysRegs from array bool to BitVector to save some space. Setting ↵Evan Cheng2007-04-251-2/+2
| | | | | | / getting its states now go through MachineFunction. llvm-svn: 36451
* Clean up.Evan Cheng2007-04-251-3/+1
| | | | llvm-svn: 36449
* Data structure change to improve compile time (especially in debug mode).Evan Cheng2007-04-251-12/+23
| | | | llvm-svn: 36447
* This was lefted out. Fixed sumarray-dbl.Evan Cheng2007-04-251-0/+1
| | | | llvm-svn: 36445
* Implement aliases. This fixes PR1017 and it's dependent bugs. CFE partAnton Korobeynikov2007-04-251-1/+25
| | | | | | will follow. llvm-svn: 36435
* Fix for PR1306.Evan Cheng2007-04-252-47/+180
| | | | | | | | | - A register def / use now implicitly affects sub-register liveness but does not affect liveness information of super-registers. - Def of a larger register (if followed by a use later) is treated as read/mod/write of a smaller register. llvm-svn: 36434
* Clean up.Evan Cheng2007-04-251-4/+2
| | | | llvm-svn: 36431
* support for >4G stack framesChris Lattner2007-04-251-1/+1
| | | | llvm-svn: 36425
* support > 4G stack objectsChris Lattner2007-04-252-3/+3
| | | | llvm-svn: 36422
* allow support for 64-bit stack objectsChris Lattner2007-04-251-1/+1
| | | | llvm-svn: 36420
* Be more careful about folding op(x, undef) when we have vector operands.Chris Lattner2007-04-251-9/+16
| | | | | | This fixes CodeGen/X86/2007-04-24-VectorCrash.ll llvm-svn: 36413
* Assertion when using a 1-element vector for an add operation. Get theBill Wendling2007-04-241-4/+7
| | | | | | real vector type in this case. llvm-svn: 36402
* Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings aboutScott Michel2007-04-241-2/+2
| | | | | | tests always being true in the process. llvm-svn: 36387
* modify per review commentaryDale Johannesen2007-04-231-2/+2
| | | | llvm-svn: 36383
* make EmitAlignment work the way Chris says it shouldDale Johannesen2007-04-231-1/+3
| | | | llvm-svn: 36368
* PR400 phase 2. Propagate attributed load/store information through DAGs.Christopher Lamb2007-04-223-36/+112
| | | | llvm-svn: 36356
* X86 TLS: Implement review feedback.Lauro Ramos Venancio2007-04-211-1/+11
| | | | llvm-svn: 36318
* Revert Christopher Lamb's load/store alignment changes.Reid Spencer2007-04-213-79/+36
| | | | llvm-svn: 36309
* add support for alignment attributes on load/store instructionsChristopher Lamb2007-04-213-36/+79
| | | | llvm-svn: 36301
* Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.Lauro Ramos Venancio2007-04-201-1/+1
| | | | llvm-svn: 36290
* Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio2007-04-202-2/+22
| | | | | | X86 32 bits. llvm-svn: 36283
* VarInfo::UsedBlocks is no longer used. Remove.Evan Cheng2007-04-184-17/+2
| | | | llvm-svn: 36250
* allow SRL to simplify its operands, as it doesn't demand all bits as input.Chris Lattner2007-04-181-1/+7
| | | | llvm-svn: 36245
* When replacing a node in SimplifyDemandedBits, if the old node used anyChris Lattner2007-04-181-1/+8
| | | | | | | single-use nodes, they will be dead soon. Make sure to remove them before processing other nodes. This implements CodeGen/X86/shl_elim.ll llvm-svn: 36244
* fix a pastoChris Lattner2007-04-181-1/+1
| | | | llvm-svn: 36242
* Don't populate TryAgainList when coalescing only physical registers with ↵Evan Cheng2007-04-181-6/+6
| | | | | | virtual registers. llvm-svn: 36240
* Increment use count of new virtuals created during PHI elimination.Evan Cheng2007-04-181-0/+3
| | | | llvm-svn: 36233
* Fix a bug in my previous patch, grabbing the shift amount width from theChris Lattner2007-04-171-2/+2
| | | | | | wrong operand. llvm-svn: 36223
* Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.Chris Lattner2007-04-171-5/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll llvm-svn: 36221
* Copy coalescing change to prevent a physical register from being pin to aEvan Cheng2007-04-172-86/+98
| | | | | | | | | | | | | long live interval that has low usage density. 1. Change order of coalescing to join physical registers with virtual registers first before virtual register intervals become too long. 2. Check size and usage density to determine if it's worthwhile to join. 3. If joining is aborted, assign virtual register live interval allocation preference field to the physical register. 4. Register allocator should try to allocate to the preferred register first (if available) to create identify moves that can be eliminated. llvm-svn: 36218
* Add a register allocation preference field; add a method to compute size of ↵Evan Cheng2007-04-171-0/+9
| | | | | | a live interval. llvm-svn: 36216
* Keep track of number of uses within the function per virtual register.Evan Cheng2007-04-171-0/+1
| | | | llvm-svn: 36214
* SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBitsChris Lattner2007-04-171-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | a chance to hack on it. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr instead of: _baz: srwi r2, r4, 24 rlwimi r2, r3, 8, 0, 23 srwi r2, r2, 9 extsh r3, r2 blr This implements CodeGen/PowerPC/sign_ext_inreg1.ll llvm-svn: 36212
* Fix problems in the PartSet lowering having to do with incorrect bit width.Reid Spencer2007-04-161-3/+5
| | | | llvm-svn: 36180
* Removed tabs everywhere except autogenerated & external files. Add makeAnton Korobeynikov2007-04-164-47/+47
| | | | | | target for tabs checking. llvm-svn: 36146
* disable switch lowering using shift/and. It still breaks ppc bootstrap forChris Lattner2007-04-141-0/+1
| | | | | | some reason. :( Will investigate. llvm-svn: 36011
* Fix PR1325: Case range optimization was performed in the case itAnton Korobeynikov2007-04-141-4/+2
| | | | | | shouldn't. Also fix some "latent" bug on 64-bit platforms llvm-svn: 35990
* disable shift/and lowering to work around PR1325 for now.Chris Lattner2007-04-141-1/+3
| | | | llvm-svn: 35985
* Fix PR1323 : we haven't updated phi nodes in good manner :)Anton Korobeynikov2007-04-131-0/+1
| | | | llvm-svn: 35963
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