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* Make sure intrinsics that are lowered to functions make the function weakReid Spencer2007-04-121-2/+2
| | | | | | | linkage so we only end up with one of them in a program. These are, after all overloaded and templatish in nature. llvm-svn: 35956
* Fix bugs in generated code for part_select and part_set so that llc doesn'tReid Spencer2007-04-121-35/+44
| | | | | | barf when CBE is run with a program that contains these intrinsics. llvm-svn: 35946
* Fix a bug in PartSet. The replacement value needs to be zext or trunc toReid Spencer2007-04-121-3/+7
| | | | | | the size of the value, not just zext. Also, give better names to two BBs. llvm-svn: 35945
* the result of an inline asm copy can be an arbitrary VT that the registerChris Lattner2007-04-121-4/+21
| | | | | | | | class supports. In the case of vectors, this means we often get the wrong type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector result to the right type. This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll llvm-svn: 35944
* fold noop vbitconvert instructionsChris Lattner2007-04-121-0/+9
| | | | llvm-svn: 35943
* Fix weirdness handling single element vectors.Chris Lattner2007-04-121-5/+2
| | | | llvm-svn: 35941
* For PR1284:Reid Spencer2007-04-122-12/+199
| | | | | | Implement the "part_set" intrinsic. llvm-svn: 35938
* fix an infinite loop compiling ldecod, notice by JeffC.Chris Lattner2007-04-111-1/+1
| | | | llvm-svn: 35910
* Fix this harder.Chris Lattner2007-04-111-12/+19
| | | | llvm-svn: 35888
* don't create shifts by zero, fix some problems with my previous patchChris Lattner2007-04-111-3/+7
| | | | llvm-svn: 35887
* Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which oftenChris Lattner2007-04-111-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allows other simplifications. For example, this compiles: int isnegative(unsigned int X) { return !(X < 2147483648U); } Into this code: x86: movl 4(%esp), %eax shrl $31, %eax ret arm: mov r0, r0, lsr #31 bx lr thumb: lsr r0, r0, #31 bx lr instead of: x86: cmpl $0, 4(%esp) sets %al movzbl %al, %eax ret arm: mov r3, #0 cmp r0, #0 movlt r3, #1 mov r0, r3 bx lr thumb: mov r2, #1 mov r1, #0 cmp r0, #0 blt LBB1_2 @entry LBB1_1: @entry cpy r2, r1 LBB1_2: @entry cpy r0, r2 bx lr Testcase here: test/CodeGen/Generic/ispositive.ll llvm-svn: 35883
* Codegen integer abs more efficiently using the trick from the PPC CWG. ThisChris Lattner2007-04-111-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll X86 Old: X86 New: _test: _test: movl 4(%esp), %ecx movl 4(%esp), %eax movl %ecx, %eax movl %eax, %ecx negl %eax sarl $31, %ecx testl %ecx, %ecx addl %ecx, %eax cmovns %ecx, %eax xorl %ecx, %eax ret ret PPC Old: PPC New: _test: _test: cmpwi cr0, r3, -1 srawi r2, r3, 31 neg r2, r3 add r3, r3, r2 bgt cr0, LBB1_2 ; xor r3, r3, r2 LBB1_1: ; blr mr r3, r2 LBB1_2: ; blr ARM Old: ARM New: _test: _test: rsb r3, r0, #0 add r3, r0, r0, asr #31 cmp r0, #0 eor r0, r3, r0, asr #31 movge r3, r0 bx lr mov r0, r3 bx lr Thumb Old: Thumb New: _test: _test: neg r2, r0 asr r2, r0, #31 cmp r0, #0 add r0, r0, r2 bge LBB1_2 eor r0, r2 LBB1_1: @ bx lr cpy r0, r2 LBB1_2: @ bx lr Sparc Old: Sparc New: test: test: save -96, %o6, %o6 save -96, %o6, %o6 sethi 0, %l0 sra %i0, 31, %l0 sub %l0, %i0, %l0 add %i0, %l0, %l1 subcc %i0, -1, %l1 xor %l1, %l0, %i0 bg .BB1_2 restore %g0, %g0, %g0 nop retl .BB1_1: nop or %g0, %l0, %i0 .BB1_2: restore %g0, %g0, %g0 retl nop It also helps alpha/ia64 :) llvm-svn: 35881
* For PR1146:Reid Spencer2007-04-111-13/+13
| | | | | | | Put the parameter attributes in their own ParamAttr name space. Adjust the rest of llvm as a result. llvm-svn: 35877
* apparently some people commit without building the tree, or they forget toChris Lattner2007-04-102-2/+2
| | | | | | commit a LOT of files. llvm-svn: 35858
* No longer needed.Jeff Cohen2007-04-091-1/+0
| | | | llvm-svn: 35850
* remove dead target hooks.Chris Lattner2007-04-091-19/+0
| | | | llvm-svn: 35847
* remove some dead target hooks, subsumed by isLegalAddressingModeChris Lattner2007-04-091-17/+0
| | | | llvm-svn: 35840
* Use integer log for metric calculationAnton Korobeynikov2007-04-091-2/+2
| | | | llvm-svn: 35834
* Unbreak VC++ build.Jeff Cohen2007-04-091-2/+3
| | | | llvm-svn: 35817
* Next stage into switch lowering refactoringAnton Korobeynikov2007-04-091-19/+340
| | | | | | | | | | 1. Fix some bugs in the jump table lowering threshold 2. Implement much better metric for optimal pivot selection 3. Tune thresholds for different lowering methods 4. Implement shift-and trick for lowering small (<machine word length) cases with few destinations. Good testcase will follow. llvm-svn: 35816
* For PR1146:Reid Spencer2007-04-091-13/+17
| | | | | | Adapt handling of parameter attributes to use the new ParamAttrsList class. llvm-svn: 35814
* implement CodeGen/X86/inline-asm-x-scalar.ll:test3Chris Lattner2007-04-091-2/+9
| | | | llvm-svn: 35802
* add some assertionsChris Lattner2007-04-091-0/+13
| | | | llvm-svn: 35800
* Fix a bug introduced with my previous patch, where it didn't correctly handleChris Lattner2007-04-091-7/+9
| | | | | | | instructions which replace themselves when FI's are rewritten (common on ppc). This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll llvm-svn: 35789
* Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308:Chris Lattner2007-04-091-1/+5
| | | | | | | some instructions can have multiple frame indices in them. If this happens, rewrite all of them. llvm-svn: 35785
* Fix PR1316Chris Lattner2007-04-091-4/+4
| | | | llvm-svn: 35783
* Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314Chris Lattner2007-04-081-1/+1
| | | | llvm-svn: 35779
* minor comment fixChris Lattner2007-04-061-1/+1
| | | | llvm-svn: 35696
* Change the bit_part_select (non)implementation from "return 0" to abort.Reid Spencer2007-04-051-3/+5
| | | | llvm-svn: 35679
* Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.Reid Spencer2007-04-042-0/+180
| | | | llvm-svn: 35678
* Properly emit range comparisons for switch cases, where neighbour casesAnton Korobeynikov2007-04-041-71/+181
| | | | | | | go to the same destination. Now we're producing really good code for switch-lower-feature.ll testcase llvm-svn: 35672
* Re-materialize all loads from fixed stack slots.Evan Cheng2007-04-043-15/+34
| | | | llvm-svn: 35660
* Trivially re-materializable instructions have spill weights that are half of ↵Evan Cheng2007-04-041-6/+6
| | | | | | what it would be otherwise. llvm-svn: 35658
* Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found.Evan Cheng2007-04-031-1/+1
| | | | llvm-svn: 35618
* 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.Scott Michel2007-04-022-25/+76
| | | | | | | | | 2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL patterns. This was motivated by the X86/rotate.ll testcase, which should now generate code for other platforms (and soon-to-come platforms.) Rewrote code slightly to make it easier to read. llvm-svn: 35605
* Ugh. Copy coalescer does not update register numbers.Evan Cheng2007-04-021-2/+15
| | | | llvm-svn: 35600
* For PR1297:Reid Spencer2007-04-021-1/+1
| | | | | | | Make sure that the CTPOP result is casted to i32 as the bit counting intrinsics all return i32 now (this affects CTLZ and CTTZ as well). llvm-svn: 35567
* For PR1297:Reid Spencer2007-04-011-17/+4
| | | | | | Support overloaded intrinsics bswap, ctpop, cttz, ctlz. llvm-svn: 35547
* For PR1297:Reid Spencer2007-04-011-24/+31
| | | | | | | Adjust for changes in the bit counting intrinsics. They all return i32 now so we have to trunc/zext the DAG node accordingly. llvm-svn: 35546
* For PR1297:Reid Spencer2007-04-011-1/+1
| | | | | | Change getOperationName to return std::string instead of const char* llvm-svn: 35545
* move a bunch of code out of the sdisel pass into its own opt pass ↵Chris Lattner2007-03-312-485/+21
| | | | | | "codegenprepare". llvm-svn: 35529
* switch TL::getValueType to use MVT::getValueType.Chris Lattner2007-03-311-22/+0
| | | | llvm-svn: 35527
* Add a -print-lsr-output option to LLC, to print the output of the LSR pass.Chris Lattner2007-03-311-1/+9
| | | | llvm-svn: 35522
* add one addressing mode description hook to rule them all.Chris Lattner2007-03-301-0/+34
| | | | llvm-svn: 35520
* Fix incorrect combination of different loads. Reenable zext-over-truncateDale Johannesen2007-03-302-75/+71
| | | | | | combination. llvm-svn: 35517
* Don't add the same MI to register reuse "last def/use" twice if it reads theEvan Cheng2007-03-301-1/+4
| | | | | | register more than once. llvm-svn: 35513
* Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep lengthEvan Cheng2007-03-301-5/+10
| | | | | | | | of dead def live interval at 1 to avoid multiple def's targeting the same register. The previous patch missed a case where the source operand is live-in. In that case, remove the whole interval. llvm-svn: 35512
* Disable load width reduction xform of variant (zext (truncate load x)) forEvan Cheng2007-03-291-1/+3
| | | | | | big endian targets until llvm-gcc build issue has been resolved. llvm-svn: 35449
* New entries.Evan Cheng2007-03-291-0/+21
| | | | llvm-svn: 35445
* Notes on re-materialization.Evan Cheng2007-03-281-0/+40
| | | | llvm-svn: 35420
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