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* Fix thinko - the operand number has nothing to doDuncan Sands2008-10-232-3/+3
| | | | | | with the result number. llvm-svn: 58041
* LegalizeTypes soft-float support for fpow.Duncan Sands2008-10-222-1/+15
| | | | llvm-svn: 57973
* Be nice to CellSPU: for this target getSetCCResultTypeDuncan Sands2008-10-221-2/+8
| | | | | | | | | | | | may return i8, which can result in SELECT nodes for which the type of the condition is i8, but there are no patterns for select with i8 condition. Tweak the LegalizeTypes logic to avoid this as much as possible. This isn't a real fix because it is still perfectly possible to end up with such select nodes - CellSPU needs to be fixed IMHO. llvm-svn: 57968
* Port from LegalizeDAG the logic to only generateDuncan Sands2008-10-221-8/+44
| | | | | | ADDC/ADDE/SUBC/SUBE if the target supports it. llvm-svn: 57967
* Add some comments explaining the meaning of a booleanDuncan Sands2008-10-221-4/+2
| | | | | | | | that is not of type MVT::i1 in SELECT and SETCC nodes. Relax the LegalizeTypes SELECT condition promotion sanity checks to allow other condition types than i1. llvm-svn: 57966
* Temporarily allow the operands of a BUILD_VECTORDuncan Sands2008-10-221-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | to have a different type to the vector element type. This should be fairly harmless because in the past guys like this were being built all over the place (and were cleaned up when I added this check). The reason for relaxing this check is that it helps LegalizeTypes legalize vector shuffles: the mask is a BUILD_VECTOR that it is *not always possible* to legalize while keeping it a BUILD_VECTOR (vector_shuffle requires the mask to be a BUILD_VECTOR, as opposed to a vector with the right vector type). With this check it is even harder to legalize the mask - turning the check off means that LegalizeTypes manages to legalize almost all vector shuffles encountered in practice. The correct solution is to change vector_shuffle to be a variadic node with the mask built into it as operands. While waiting for that change, this hack stops the problem with vector_shuffle from blocking the turning on of LegalizeTypes. llvm-svn: 57965
* Move Print*Pass to use raw_ostream.Daniel Dunbar2008-10-221-2/+2
| | | | llvm-svn: 57946
* Privatize PrintModulePass and PrintFunctionPass and addDaniel Dunbar2008-10-211-3/+4
| | | | | | | createPrintModulePass and createPrintFunctionPass. - So clients who compile w/o RTTI can use them. llvm-svn: 57933
* Add an SSE2 algorithm for uint64->f64 conversion.Dale Johannesen2008-10-211-0/+16
| | | | | | | | | | The same one Apple gcc uses, faster. Also gets the extreme case in gcc.c-torture/execute/ieee/rbug.c correct which we weren't before; this is not sufficient to get the test to pass though, there is another bug. llvm-svn: 57926
* Fix SelectionDAGBuild lowering of Select instructions toDan Gohman2008-10-211-8/+22
| | | | | | | handle first-class aggregate values. Also, fix a bug in the Ret handling for empty aggregates. llvm-svn: 57925
* Don't create TargetGlobalAddress nodes with offsets that don't fitDan Gohman2008-10-211-1/+1
| | | | | | | | | | | | | | in the 32-bit signed offset field of addresses. Even though this may be intended, some linkers refuse to relocate code where the relocated address computation overflows. Also, fix the sign-extension of constant offsets to use the actual pointer size, rather than the size of the GlobalAddress node, which may be different, for example on x86-64 where MVT::i32 is used when the address is being fit into the 32-bit displacement field. llvm-svn: 57885
* Optimized FCMP_OEQ and FCMP_UNE for x86.Dan Gohman2008-10-211-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
* When the coalescer is doing rematerializing, have it removeDan Gohman2008-10-211-2/+3
| | | | | | | | | | | | | | | | | | | | the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. llvm-svn: 57872
* Make the NaN test come second, heuristically assumingDan Gohman2008-10-211-12/+12
| | | | | | that NaNs are less common. llvm-svn: 57871
* CMake: updated lib/CodeGen/CMakeLists.txtOscar Fuentes2008-10-211-0/+1
| | | | llvm-svn: 57869
* Fix gcc.c-torture/compile/920520-1.c by inserting bitconvertsChris Lattner2008-10-211-7/+30
| | | | | | | | | for strange asm conditions earlier. In this case, we have a double being passed in an integer reg class. Convert to like sized integer register so that we allocate the right number for the class (two i32's for the f64 in this case). llvm-svn: 57862
* Add skeleton for the pre-register allocation live interval splitting pass.Evan Cheng2008-10-201-0/+81
| | | | llvm-svn: 57847
* Fast-isel no longer an experiment.Dan Gohman2008-10-201-1/+1
| | | | llvm-svn: 57845
* Add a register class -> virtual registers map.Evan Cheng2008-10-201-0/+1
| | | | llvm-svn: 57844
* Support operations like fp_to_uint with a vectorDuncan Sands2008-10-202-1/+53
| | | | | | | | | result type when the result type is legal but not the operand type. Add additional support for EXTRACT_SUBVECTOR and CONCAT_VECTORS, needed to handle such cases. llvm-svn: 57840
* LegalizeTypes support for atomic operation promotion.Duncan Sands2008-10-202-3/+78
| | | | llvm-svn: 57838
* Use DAG.getIntPtrConstant rather than DAG.getConstantDuncan Sands2008-10-202-6/+4
| | | | | | with TLI.getPointerTy for a small simplification. llvm-svn: 57837
* Always use either MVT::i1 or getSetCCResultType forDuncan Sands2008-10-201-15/+51
| | | | | | | | the condition of a SELECT node. Make sure that the correct extension type (any-, sign- or zero-extend) is used. llvm-svn: 57836
* Formatting - no functional change.Duncan Sands2008-10-202-7/+6
| | | | llvm-svn: 57834
* Don't use a random type for the select condition,Duncan Sands2008-10-201-2/+1
| | | | | | use an MVT::i1 and simplify the code while there. llvm-svn: 57833
* Set N->OperandList to 0 after deletion. Otherwise, it's possible that it willBill Wendling2008-10-191-15/+26
| | | | | | be either deleted or referenced afterwards. llvm-svn: 57786
* Fix comment. Other formatting changes. No functionality changes.Bill Wendling2008-10-191-5/+6
| | | | llvm-svn: 57785
* Vector shuffle mask elements may be "undef". HandleDuncan Sands2008-10-191-13/+24
| | | | | | this everywhere in LegalizeTypes. llvm-svn: 57783
* Use a legal integer type for vector shuffle maskDuncan Sands2008-10-191-4/+4
| | | | | | | | | elements. Otherwise LegalizeTypes will, reasonably enough, legalize the mask, which may result in it no longer being a BUILD_VECTOR node (LegalizeDAG simply ignores the legality or not of vector masks). llvm-svn: 57782
* Reapply r57699 with a fix to not crash on asms with multiple results. UnlikeChris Lattner2008-10-181-16/+48
| | | | | | | | | | the previous patch this one actually passes make check. "Fix PR2356 on PowerPC: if we have an input and output that are tied together that have different sizes (e.g. i32 and i64) make sure to reserve registers for the bigger operand." llvm-svn: 57771
* Don't truncate GlobalAddress offsets to int in debug output.Dan Gohman2008-10-182-2/+2
| | | | llvm-svn: 57770
* By min, I mean max.Evan Cheng2008-10-181-1/+1
| | | | llvm-svn: 57766
* When creating intervals, leave min(1, numdefs) holes after each instruction.Evan Cheng2008-10-181-5/+13
| | | | llvm-svn: 57765
* Teach DAGCombine to fold constant offsets into GlobalAddress nodes,Dan Gohman2008-10-183-2/+47
| | | | | | | | | | | | | | | | | | | | | | and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
* Revert r57699. It's causing regressions inDan Gohman2008-10-181-43/+15
| | | | | | | test/CodeGen/X86/2008-09-17-inline-asm-1.ll and a few others, and it breaks the llvm-gcc build. llvm-svn: 57747
* Factor out the code for mapping LLVM IR condition opcodes toDan Gohman2008-10-172-34/+47
| | | | | | ISD condition opcodes into helper functions. llvm-svn: 57726
* Fix PR2898. Spiller delete a store for reuse before it knows for sure the ↵Evan Cheng2008-10-171-11/+26
| | | | | | | | reuse happened. Patch by Lang Hames! llvm-svn: 57720
* add support for 128 bit aggregates.Chris Lattner2008-10-171-0/+1
| | | | llvm-svn: 57715
* The Dwarf writer was comparing mangled and unmangled names for C++ code when weBill Wendling2008-10-171-1/+4
| | | | | | | | | have an unreachable block in a function. This was triggering the assert. This is a horrid hack to cover this up. Oh! for a good debug info architecture! llvm-svn: 57714
* Added MemIntrinsicNode which is useful to represent target intrinsics thatMon P Wang2008-10-171-2/+59
| | | | | | touches memory and need an associated MemOperand llvm-svn: 57712
* Factor out the code for mapping LLVM IR condition opcodes toDan Gohman2008-10-171-126/+61
| | | | | | ISD condition opcodes into helper functions. llvm-svn: 57710
* Fix PR2356 on PowerPC: if we have an input and output that are tied togetherChris Lattner2008-10-171-15/+43
| | | | | | | that have different sizes (e.g. i32 and i64) make sure to reserve registers for the bigger operand. llvm-svn: 57699
* refactor some code into a helper method, no functionality change.Chris Lattner2008-10-171-25/+40
| | | | llvm-svn: 57690
* Keep track of *which* input constraint matches an outputChris Lattner2008-10-172-6/+6
| | | | | | | constraint. Reject asms where an output has multiple input constraints tied to it. llvm-svn: 57687
* add an assert so that PR2356 explodes instead of running off anChris Lattner2008-10-172-6/+24
| | | | | | | array. Improve some minor comments, refactor some helpers in AsmOperandInfo. No functionality change for valid code. llvm-svn: 57686
* Fix a very subtle spiller bug: UpdateKills should not forget to track defs ↵Evan Cheng2008-10-171-8/+14
| | | | | | of aliases. llvm-svn: 57673
* Define patterns for shld and shrd that match immediateDan Gohman2008-10-171-5/+9
| | | | | | | | | | | | | | | | | | shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
* Rename AliasSet to SubRegs, to reflect changes in the surrounding code.Dan Gohman2008-10-161-3/+3
| | | | llvm-svn: 57618
* Move the include of MachineLocation.h into MachineModuleInfo.hDan Gohman2008-10-161-1/+0
| | | | | | | | because it declares a std::vector<MachineMove>, and strict concept checking requires the definition of MachineMove to be available. llvm-svn: 57617
* Fix a subtle bug in DeadMachineInstructionElim's livenessDan Gohman2008-10-161-1/+4
| | | | | | | computation. A def of a register doesn't necessarily kill live super-registers. llvm-svn: 57614
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