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authorChris Lattner <sabre@nondot.org>2008-10-17 16:47:46 +0000
committerChris Lattner <sabre@nondot.org>2008-10-17 16:47:46 +0000
commit860df6e84c9f737b8d17b62308dc14fa8084de78 (patch)
treea84f0a289962621e233eafea4d79d990096e0f1b /llvm/lib/CodeGen
parentef8901722eb2d48531b9cc06fffba2511fe32d46 (diff)
downloadbcm5719-llvm-860df6e84c9f737b8d17b62308dc14fa8084de78.tar.gz
bcm5719-llvm-860df6e84c9f737b8d17b62308dc14fa8084de78.zip
Keep track of *which* input constraint matches an output
constraint. Reject asms where an output has multiple input constraints tied to it. llvm-svn: 57687
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp6
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp6
2 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 64192dc41ae..103b5c0e7e7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -4491,7 +4491,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
// If there is an input constraint that matches this, we need to reserve
// the input register so no other inputs allocate to it.
- isInReg = OpInfo.hasMatchingInput;
+ isInReg = OpInfo.hasMatchingInput();
break;
case InlineAsm::isInput:
isInReg = true;
@@ -4562,7 +4562,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
// the constraint, so we have to pick a register to pin the input/output to.
// If it isn't a matched constraint, go ahead and create vreg and let the
// regalloc do its thing.
- if (!OpInfo.hasMatchingInput) {
+ if (!OpInfo.hasMatchingInput()) {
RegVT = *PhysReg.second->vt_begin();
if (OpInfo.ConstraintVT == MVT::Other)
ValueVT = RegVT;
@@ -4863,7 +4863,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
case InlineAsm::isInput: {
SDValue InOperandVal = OpInfo.CallOperand;
- if (OpInfo.isMatchingConstraint()) { // Matching constraint?
+ if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
// If this is required to match an output register we have already set,
// just use its register.
unsigned OperandNo = OpInfo.getMatchedOperand();
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 664e06d2d27..479e1380c5b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1962,9 +1962,9 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
//===----------------------------------------------------------------------===//
// Constraint Selection.
-/// isMatchingConstraint - Return true of this is an input operand that is a
-/// matching constraint like "4".
-bool TargetLowering::AsmOperandInfo::isMatchingConstraint() const {
+/// isMatchingInputConstraint - Return true of this is an input operand that is
+/// a matching constraint like "4".
+bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
assert(!ConstraintCode.empty() && "No known constraint!");
return isdigit(ConstraintCode[0]);
}
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