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* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-0610-82/+123
| | | | | | | | | | | | with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
* Split the init.trampoline intrinsic, which currently combines GCC'sDuncan Sands2011-09-063-7/+12
| | | | | | | | | | | | | | | | | | | | init.trampoline and adjust.trampoline intrinsics, into two intrinsics like in GCC. While having one combined intrinsic is tempting, it is not natural because typically the trampoline initialization needs to be done in one function, and the result of adjust trampoline is needed in a different (nested) function. To get around this llvm-gcc hacks the nested function lowering code to insert an additional parent variable holding the adjust.trampoline result that can be accessed from the child function. Dragonegg doesn't have the luxury of tweaking GCC code, so it stored the result of adjust.trampoline in the memory GCC set aside for the trampoline itself (this is always available in the child function), and set up some new memory (using an alloca) to hold the trampoline. Unfortunately this breaks Go which allocates trampoline memory on the heap and wants to use it even after the parent has exited (!). Rather than doing even more hacks to get Go working, it seemed best to just use two intrinsics like in GCC. Patch mostly by Sanjoy Das. llvm-svn: 139140
* Fix a truly heinous bug in DAGCombine related to AssertZext.Owen Anderson2011-09-031-7/+6
| | | | | | | If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem. Fixes <rdar://problem/10063365>. llvm-svn: 139059
* Simplify by using isFullCopy().Jakob Stoklund Olesen2011-09-021-3/+1
| | | | llvm-svn: 139019
* Darwin wants ctors/dtors to be ordered the other way round to linux.Duncan Sands2011-09-021-1/+10
| | | | llvm-svn: 139015
* Revert r131152, r129796, r129761. This code is currently consideredDan Gohman2011-09-011-52/+43
| | | | | | | | to be unreliable on platforms which require memcpy calls, and it is complicating broader legalize cleanups. It is hoped that these cleanups will make memcpy byval easier to implement in the future. llvm-svn: 138977
* Don't drop alignment info on local common symbols.Benjamin Kramer2011-09-011-5/+5
| | | | | | | | | | | - On COFF the .lcomm directive has an alignment argument. - On ELF we fall back to .local + .comm Based on a patch by NAKAMURA Takumi. Fixes PR9337, PR9483 and PR10128. llvm-svn: 138976
* Permit remat of partial register defs when it is safe.Jakob Stoklund Olesen2011-09-011-5/+10
| | | | | | | | | | | | | | | | | An instruction may define part of a register where the other bits are undefined. In that case, it is safe to rematerialize the instruction. For example: %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def> The extra <imp-def> operand indicates that the instruction does not read the other parts of the virtual register, so a remat is safe. This patch simply allows multiple def operands for the virtual register. It is MI->readsVirtualRegister() that determines if we depend on a previous value so remat is impossible. llvm-svn: 138953
* Revert r138794, "Do not try to rematerialize a value from a partial definition."Jakob Stoklund Olesen2011-09-011-22/+1
| | | | | | | | | The problem is fixed for all register allocators by r138944, so this patch is no longer necessary. <rdar://problem/10032939> llvm-svn: 138945
* Prevent remat of partial register redefinitions.Jakob Stoklund Olesen2011-09-011-0/+9
| | | | | | | | | | | | | An instruction that redefines only part of a larger register can never be rematerialized since the virtual register value depends on the old value in other parts of the register. This was fixed for the inline spiller in r138794. This patch fixes the problem for all register allocators, and includes a small test case. <rdar://problem/10032939> llvm-svn: 138944
* Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. ↵Evan Cheng2011-09-011-27/+40
| | | | | | Sorry, I can't come up with a small test case. rdar://10043690 llvm-svn: 138934
* PreRA scheduler should avoid cloning compares.Andrew Trick2011-09-011-1/+35
| | | | | | | | | Added canClobberReachingPhysRegUse() to handle a particular pattern in which a two-address instruction could be forced to interfere with EFLAGS, causing a compare to be unnecessarilly cloned. Fixes rdar://problem/5875261 llvm-svn: 138924
* Fix Size TypingDavid Greene2011-08-311-1/+1
| | | | | | Stores sizes as uint64_t to avoid possible truncation. llvm-svn: 138901
* Misc cleanup; addresses Duncan's comments on r138877.Eli Friedman2011-08-314-22/+17
| | | | llvm-svn: 138887
* Fill in type legalization for MERGE_VALUES in all the various cases. Patch ↵Eli Friedman2011-08-316-18/+77
| | | | | | by Micah Villmow. (No testcase because the issue only showed up in an out-of-tree backend.) llvm-svn: 138877
* Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; ↵Eli Friedman2011-08-312-0/+33
| | | | | | implements 64-bit atomic load/store for ARM. llvm-svn: 138872
* Compress Repeated Byte OutputDavid Greene2011-08-311-3/+59
| | | | | | | Emit a repeated sequence of bytes using .zero. This saves an enormous amount of asm file space for certain programs. llvm-svn: 138864
* Spelling and grammar fixes to problems found by Duncan.Rafael Espindola2011-08-311-4/+4
| | | | llvm-svn: 138858
* Emit segmented-stack specific code into function prologues forRafael Espindola2011-08-301-0/+8
| | | | | | | | | | | | X86. Modify the pass added in the previous patch to call this new code. This new prologues generated will call a libgcc routine (__morestack) to allocate more stack space from the heap when required Patch by Sanjoy Das. llvm-svn: 138812
* Follow up to r138791.Evan Cheng2011-08-302-0/+14
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Do not try to rematerialize a value from a partial definition.Bob Wilson2011-08-301-1/+22
| | | | | | | I don't currently have a good testcase for this; will try to get one tomorrow. <rdar://problem/10032939> llvm-svn: 138794
* Thumb2 parsing and encoding for IT blocks.Jim Grosbach2011-08-291-0/+4
| | | | llvm-svn: 138773
* Fix PR5329: pay attention to constructor/destructor priorityDuncan Sands2011-08-281-13/+36
| | | | | | | when outputting them. With this, the entire LLVM testsuite passes when built with dragonegg. llvm-svn: 138724
* These splits should be done whether they are critical edges or not.Bill Wendling2011-08-271-16/+8
| | | | llvm-svn: 138697
* Update the dominator tree with the correct dominator for the new 'unwind' block.Bill Wendling2011-08-261-0/+5
| | | | llvm-svn: 138664
* Split the landing pad block only if it's a critical edge. Also intelligentlyBill Wendling2011-08-261-5/+21
| | | | | | split it in the other place where we're splitting critical edges. llvm-svn: 138658
* Atomic load/store on ARM/Thumb.Eli Friedman2011-08-262-5/+27
| | | | | | | | | | | | I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
* Look at only the terminators of the basic block. Also, if we're using the new EHBill Wendling2011-08-251-5/+9
| | | | | | | scheme, return 'true' so that it doesn't try to run the old EH scheme's fixup on the new code. llvm-svn: 138605
* Basic x86 code generation for atomic load and store instructions.Eli Friedman2011-08-244-12/+147
| | | | llvm-svn: 138478
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-242-2/+2
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Tidy up. Trailing whitespace.Jim Grosbach2011-08-241-31/+31
| | | | llvm-svn: 138437
* Add the sentinal "no handle" value to the ResumeInst.Bill Wendling2011-08-241-0/+2
| | | | | | | | A value of -1 at a call site tells the personality function that this call isn't handled by the current function. Since the ResumeInsts are converted to calls to _Unwind_SjLj_Resume, add a (volatile) store of -1 to its 'call site'. llvm-svn: 138416
* Don't replace *all* uses with the new stuff.Bill Wendling2011-08-231-1/+1
| | | | | | | | This is not necessarily the first or dominating use of the EH values. The IR breaks if it's not. So replace the specific value in the instruction with the new value. llvm-svn: 138406
* Look at the end of the entry block for an invoke.Bill Wendling2011-08-231-4/+17
| | | | | | | | The invoke could be at the end of the entry block. If it's the only one, then we won't process all of the landingpad instructions correctly. This code is currently ugly, but should be made much nicer once the new EH switch is thrown. llvm-svn: 138397
* A landingpad instruction is neither folded nor dead.Bill Wendling2011-08-231-0/+1
| | | | llvm-svn: 138387
* Fix 80 col violations.Evan Cheng2011-08-231-2/+4
| | | | llvm-svn: 138356
* Split the landing pad's edge. Then for all uses of a landingpad instruction'sBill Wendling2011-08-221-2/+74
| | | | | | | | | | value, we insert a load of the exception object and selector object from memory, which is where it actually resides. If it's used by a PHI node, we follow that to where it is being used. Eventually, all landingpad instructions should have no uses. Any PHI nodes that were associated with those landingpads should be removed. llvm-svn: 138302
* Follow up to Jim's r138278. This fixes commuteInstruction so it handles ↵Evan Cheng2011-08-221-10/+12
| | | | | | two-address instructions correctly. I'll let Jim add a test case. :-) llvm-svn: 138289
* Some whitespace fixes and #include reordering.Bill Wendling2011-08-221-8/+5
| | | | llvm-svn: 138256
* Be less redundant.Nick Lewycky2011-08-221-1/+0
| | | | llvm-svn: 138252
* Do not use named md nodes to track variables that are completely optimized. ↵Devang Patel2011-08-191-36/+23
| | | | | | This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly. llvm-svn: 138145
* Roll back the rest of r126557. It's a hack that will break in some obscure ↵Benjamin Kramer2011-08-191-6/+0
| | | | | | cases. llvm-svn: 138130
* Eli points out that this is what report_fatal_error() is for.Nick Lewycky2011-08-191-1/+2
| | | | llvm-svn: 138091
* This is not actually unreachable, so don't use llvm_unreachable for it. SinceNick Lewycky2011-08-191-1/+2
| | | | | | | | | | the intent seems to be to terminate even in Release builds, just use abort() directly. If program flow ever reaches a __builtin_unreachable (which llvm_unreachable is #define'd to on newer GCCs) then the program is undefined. llvm-svn: 138068
* Add llc flags to disable machine DCE and CSE.Jakob Stoklund Olesen2011-08-191-2/+8
| | | | | | This is useful for unit tests. llvm-svn: 138028
* Make a bunch of symbols private.Benjamin Kramer2011-08-192-2/+2
| | | | llvm-svn: 138025
* Don't treat a partial <def,undef> operand as a read.Jakob Stoklund Olesen2011-08-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | Normally, a partial register def is treated as reading the super-register unless it also defines the full register like this: %vreg110:sub_32bit<def> = COPY %vreg77:sub_32bit, %vreg110<imp-def> This patch also uses the <undef> flag on partial defs to recognize non-reading operands: %vreg110:sub_32bit<def,undef> = COPY %vreg77:sub_32bit This fixes a subtle bug in RegisterCoalescer where LIS->shrinkToUses would treat a coalesced copy as still reading the register, extending the live range artificially. My test case only works when I disable DCE so a dead copy is left for RegisterCoalescer, so I am not including it. <rdar://problem/9967101> llvm-svn: 138018
* add the comments of each declaration follow it, making it easier to read and ↵Renato Golin2011-08-181-49/+44
| | | | | | compare to GCC's result. llvm-svn: 138009
* Eliminate unnecessary forwarding function.Devang Patel2011-08-183-19/+6
| | | | llvm-svn: 138006
* Add new DIE into the map asap.Devang Patel2011-08-181-8/+6
| | | | llvm-svn: 137998
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