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authorEvan Cheng <evan.cheng@apple.com>2011-08-23 19:17:21 +0000
committerEvan Cheng <evan.cheng@apple.com>2011-08-23 19:17:21 +0000
commit6b477b985b1d9ce1ca1df975a811e83d11b80bbc (patch)
treec8fa8fd66aeabac6f53af9426ae8ad1656c09f4d /llvm/lib/CodeGen
parent4c8ff77f1bd5fc22def733b769e6fa5fd9cd3f1e (diff)
downloadbcm5719-llvm-6b477b985b1d9ce1ca1df975a811e83d11b80bbc.tar.gz
bcm5719-llvm-6b477b985b1d9ce1ca1df975a811e83d11b80bbc.zip
Fix 80 col violations.
llvm-svn: 138356
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 66a9aab76c5..41ef511b168 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5877,9 +5877,11 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
if (OpInfo.ConstraintVT != Input.ConstraintVT) {
std::pair<unsigned, const TargetRegisterClass*> MatchRC =
- TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
+ TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
+ OpInfo.ConstraintVT);
std::pair<unsigned, const TargetRegisterClass*> InputRC =
- TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
+ TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
+ Input.ConstraintVT);
if ((OpInfo.ConstraintVT.isInteger() !=
Input.ConstraintVT.isInteger()) ||
(MatchRC.second != InputRC.second)) {
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