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* Attach a GCModuleInfo to a MachineFunction.Nicolas Geoffray2010-10-312-3/+6
| | | | llvm-svn: 117867
* Include MachineBasicBlock numbers in viewCFG() output.Jakob Stoklund Olesen2010-10-301-8/+6
| | | | llvm-svn: 117765
* Make sure copies are inserted after any exception handling labels at the top ofJakob Stoklund Olesen2010-10-301-1/+1
| | | | | | a basic block. llvm-svn: 117764
* Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is neededJakob Stoklund Olesen2010-10-301-0/+7
| | | | | | elsewhere. llvm-svn: 117763
* Disable more of physical register live intervals verification.Jakob Stoklund Olesen2010-10-301-2/+3
| | | | llvm-svn: 117762
* Print out register class of spilled register.Jakob Stoklund Olesen2010-10-301-2/+4
| | | | llvm-svn: 117761
* Teach machine cse to eliminate instructions with multiple physreg uses and ↵Evan Cheng2010-10-291-50/+45
| | | | | | defs. rdar://8610857. llvm-svn: 117745
* Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson2010-10-291-5/+0
| | | | llvm-svn: 117720
* Fix sign error.Jakob Stoklund Olesen2010-10-291-1/+1
| | | | llvm-svn: 117677
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-292-24/+78
| | | | | | | | | | | | | | | | | | | | | | | | | operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. llvm-svn: 117675
* Don't transfer unused values to the new intervals formed by splitting.Jakob Stoklund Olesen2010-10-291-0/+3
| | | | llvm-svn: 117673
* Silence Release build warnings.Benjamin Kramer2010-10-291-4/+3
| | | | llvm-svn: 117671
* Teach ConnectedVNInfoEqClasses::Classify to deal with unused values.Jakob Stoklund Olesen2010-10-291-1/+15
| | | | | | | | We don't want unused values forming their own equivalence classes, so we lump them all together in one class, and then merge them with the class of the last used value. llvm-svn: 117670
* Never propagate the idom value out of a block that defines its own value.Jakob Stoklund Olesen2010-10-291-3/+7
| | | | llvm-svn: 117669
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-293-47/+77
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* This may be an ARM target, so check for _Unwind_SjLj_Resume.Bill Wendling2010-10-291-11/+15
| | | | llvm-svn: 117643
* Fix broken equivalence class calculation. We could probably also useJakob Stoklund Olesen2010-10-291-11/+8
| | | | | | | EquvivalenceClasses.h except it looks like overkill when elements are continuous integers. llvm-svn: 117631
* Print out the connected components in the verifier after complaining about theirJakob Stoklund Olesen2010-10-291-0/+8
| | | | | | multiplicity. llvm-svn: 117630
* Run a verification pass before any splitting to better distribute blame.Jakob Stoklund Olesen2010-10-291-0/+2
| | | | llvm-svn: 117629
* Ignore empty blocks.Devang Patel2010-10-281-1/+1
| | | | llvm-svn: 117615
* One day, physical register live ranges will be sensible.Jakob Stoklund Olesen2010-10-281-0/+5
| | | | llvm-svn: 117602
* Replace SplitKit SSA update with an iterative algorithm very similar to the oneJakob Stoklund Olesen2010-10-282-88/+181
| | | | | | | | | | | | | | | | in SSAUpdaterImpl.h Verifying live intervals revealed that the old method was completely wrong, and we need an iterative approach to calculating PHI placemant. Fortunately, we have MachineDominators available, so we don't have to compute that over and over like SSAUpdaterImpl.h must. Live-out values are cached between calls to mapValue() and computed in a greedy way, so most calls will be working with very small block sets. Thanks to Bob for explaining how this should work. llvm-svn: 117599
* Make MachineDominators available for SplitEditor. We are going to need it forJakob Stoklund Olesen2010-10-284-8/+21
| | | | | | | | | proper SSA updating. This doesn't cause MachineDominators to be recomputed since we are already requiring MachineLoopInfo which uses dominators as well. llvm-svn: 117598
* Add a temporary command line option to verify machine code after each spill orJakob Stoklund Olesen2010-10-281-0/+6
| | | | | | split. llvm-svn: 117597
* Do not work too hard to find type's file info. There is a special field to ↵Devang Patel2010-10-281-2/+2
| | | | | | record file info. llvm-svn: 117588
* Technically DIFile scope should also be handled here.Devang Patel2010-10-281-0/+4
| | | | llvm-svn: 117563
* Teach the DAG combiner to fold a splat of a splat. Radar 8597790.Bob Wilson2010-10-281-24/+28
| | | | | | Also do some minor refactoring to reduce indentation. llvm-svn: 117558
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-281-0/+3
| | | | llvm-svn: 117531
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng2010-10-281-3/+0
| | | | | | to fail. Ugh. llvm-svn: 117520
* Fix a major bug in operand latency computation. The use index must be adjustedEvan Cheng2010-10-281-0/+3
| | | | | | by the number of defs first for it to match the instruction itinerary. llvm-svn: 117518
* Putting r117193 back except for the compile time cost. Rather than assuming ↵Evan Cheng2010-10-271-3/+10
| | | | | | fallthroughs uses all registers, just gather the union of all successor liveins. llvm-svn: 117506
* COFF: Add IMAGE_SCN_MEM_READ to text sections.Michael J. Spencer2010-10-271-0/+1
| | | | | | | | There are currently 100 references to COFF::IMAGE_SCN in 6 files and 11 different functions. Section to attribute mapping really needs to happen in one place to avoid problems like this. llvm-svn: 117473
* Fix whitespace.Michael J. Spencer2010-10-271-15/+15
| | | | llvm-svn: 117472
* Formatting.Jim Grosbach2010-10-271-2/+2
| | | | llvm-svn: 117453
* Handle critical loop predecessors by making both inside and outside registersJakob Stoklund Olesen2010-10-272-2/+19
| | | | | | | | | live out. This doesn't prevent us from inserting a loop preheader later on, if that is better. llvm-svn: 117424
* Compute critical loop predecessors in the same way as critical loop exits.Jakob Stoklund Olesen2010-10-272-1/+38
| | | | | | | | Critical edges going into a loop are not as bad as critical exits. We can handle them by splitting the critical edge, or by having both inside and outside registers live out of the predecessor. llvm-svn: 117423
* Physical registers trivially have multiple connected components all the time.Jakob Stoklund Olesen2010-10-271-5/+7
| | | | | | Only virtuals should be requires to be connected. llvm-svn: 117422
* Use a MemIntrinsicSDNode for ISD::PREFETCH, which touchesDale Johannesen2010-10-262-2/+11
| | | | | | | | memory, so a MachineMemOperand is useful (not propagated into the MachineInstr yet). No functional change except for dump output. llvm-svn: 117413
* Remove the vector of live vregs. I thought we would need to trackAndrew Trick2010-10-262-6/+0
| | | | | | | them, but hopefully we won't. And this is not the right data structure to do it anyway. llvm-svn: 117412
* After splitting, compute connected components of all new registers, not just forJakob Stoklund Olesen2010-10-262-17/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | the remainder register. Example: bb0: x = 1 bb1: use(x) ... x = 2 jump bb1 When x is isolated in bb1, the inner part breaks into two components, x1 and x2: bb0: x0 = 1 bb1: x1 = x0 use(x1) ... x2 = 2 x0 = x2 jump bb1 llvm-svn: 117408
* Verify that live intervals are connected. If there are multiple connectedJakob Stoklund Olesen2010-10-261-1/+9
| | | | | | components, each should get its own virtual register. llvm-svn: 117407
* Call RenumberValues for all new registers created during splitting. This isJakob Stoklund Olesen2010-10-261-1/+2
| | | | | | necessary to get correct hasPHIKill flags. llvm-svn: 117406
* Preserve PHIDef bits in cloned values during splitting.Jakob Stoklund Olesen2010-10-261-0/+4
| | | | llvm-svn: 117405
* Assign source ordering to nodes created for StoreInst.Devang Patel2010-10-261-2/+5
| | | | llvm-svn: 117404
* Teach MachineBasicBlock::print() to annotate instructions and blocks withJakob Stoklund Olesen2010-10-264-20/+29
| | | | | | SlotIndexes when available. llvm-svn: 117392
* Remmeber to print full live interval on verification error.Jakob Stoklund Olesen2010-10-261-4/+7
| | | | llvm-svn: 117391
* Jakob's review of the basic register allocator.Andrew Trick2010-10-264-113/+160
| | | | llvm-svn: 117384
* s/beginScope/beginInstruction/gDevang Patel2010-10-263-10/+10
| | | | | | s/endScope/endInstruction/g llvm-svn: 117376
* Don't verify physical registers going into landing pads.Jakob Stoklund Olesen2010-10-261-0/+8
| | | | | | Magic is happening that we don't understand. llvm-svn: 117370
* Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng2010-10-261-4/+36
| | | | llvm-svn: 117348
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