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* Refactor. Variables are part of compile unit so let CompileUnit create new ↵Devang Patel2011-08-154-123/+129
| | | | | | variable. llvm-svn: 137663
* There is no need to maintain a set to keep track of variables that use ↵Devang Patel2011-08-152-8/+2
| | | | | | location expressions. In such cases, AT_location attribute's value will be a label. llvm-svn: 137659
* Fix warning.Devang Patel2011-08-152-2/+2
| | | | llvm-svn: 137658
* Simplify. Let DbgVariable keep track of variable's DBG_VALUE machine ↵Devang Patel2011-08-152-55/+24
| | | | | | instruction. llvm-svn: 137656
* Simplify mapping to variable from its abstract variable info.Devang Patel2011-08-152-29/+18
| | | | | | When a variable is inlined multiple places, abstract variable keeps name, location, type etc.. info and all other concreate instances of the variable directly refers to abstract variable. llvm-svn: 137637
* Refactor.Devang Patel2011-08-152-5/+11
| | | | llvm-svn: 137632
* Refactor.Devang Patel2011-08-152-15/+9
| | | | llvm-svn: 137631
* Refactor. Global variables are part of compile unit so let CompileUnit ↵Devang Patel2011-08-153-129/+114
| | | | | | create new global variable. llvm-svn: 137621
* Refactor. A subprogram is part of compile unit so let CompileUnit construct ↵Devang Patel2011-08-154-114/+141
| | | | | | new subprogram. llvm-svn: 137618
* Fix PR 10635. When generating integer constants, the constant element type mayNadav Rotem2011-08-131-0/+7
| | | | | | | be illegal, even if the requested vector type is legal. Testcase is one of the disabled ARM tests in the vector-select patch. llvm-svn: 137562
* Initial commit of the 'landingpad' instruction.Bill Wendling2011-08-122-0/+4
| | | | | | | | | | | | This implements the 'landingpad' instruction. It's used to indicate that a basic block is a landing pad. There are several restrictions on its use (see LangRef.html for more detail). These restrictions allow the exception handling code to gather the information it needs in a much more sane way. This patch has the definition, implementation, C interface, parsing, and bitcode support in it. llvm-svn: 137501
* Use ArrayRef.Devang Patel2011-08-121-6/+6
| | | | llvm-svn: 137485
* switch to use the new api for structtypes.Chris Lattner2011-08-121-4/+4
| | | | llvm-svn: 137480
* Provide fast path as Jakob suggested.Devang Patel2011-08-121-0/+12
| | | | llvm-svn: 137478
* Revert r137310 because it does not optimize any code on ToTNadav Rotem2011-08-121-32/+0
| | | | llvm-svn: 137466
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-126-3/+7
| | | | | | when building with assertions disabled. llvm-svn: 137460
* Simplify the interference checking code a bit.Jakob Stoklund Olesen2011-08-122-112/+42
| | | | | | | This is possible now that we now longer provide an interface to iterate the interference overlaps. llvm-svn: 137397
* Remove the InterferenceResult class.Jakob Stoklund Olesen2011-08-111-32/+0
| | | | llvm-svn: 137381
* Eliminate the last use of InterferenceResult.Jakob Stoklund Olesen2011-08-112-63/+57
| | | | | | | | The Query class now holds two iterators instead of an InterferenceResult instance. The iterators are used as bookmarks for repeated collectInterferingVRegs calls. llvm-svn: 137380
* Remove more dead code.Jakob Stoklund Olesen2011-08-112-37/+3
| | | | | | | collectInterferingVRegs will be the primary function for interference checks. llvm-svn: 137354
* Privatize an unused part of the LiveIntervalUnion::Query interface.Jakob Stoklund Olesen2011-08-112-19/+13
| | | | | | No clients are iterating over interference overlaps. llvm-svn: 137350
* Remove some dead code.Jakob Stoklund Olesen2011-08-112-39/+0
| | | | | | | | The InterferenceResult iterator turned out to be less important than we thought it would be. LiveIntervalUnion clients want higher level information, like the list of interfering virtual registers. llvm-svn: 137346
* Plug a memory leak.Benjamin Kramer2011-08-111-3/+3
| | | | llvm-svn: 137321
* [AVX] When joining two XMM registers into a YMM register, make sure that theNadav Rotem2011-08-111-0/+32
| | | | | | | lower XMM register gets in first. This will allow the SUBREG pattern to elliminate the first vector insertion. llvm-svn: 137310
* fix PR10605 / rdar://9930964 by adding a pretty scary missed check.Chris Lattner2011-08-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | It's somewhat surprising anything works without this. Before we would compile the testcase into: test: # @test movl $4, 8(%rdi) movl 8(%rdi), %eax orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 now we produce: test: # @test movl 8(%rdi), %eax movl $4, 8(%rdi) orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 llvm-svn: 137303
* Stay within 80 columns.Devang Patel2011-08-102-22/+34
| | | | llvm-svn: 137283
* Distinguish between two copies of one inlined variable. Take 2.Devang Patel2011-08-101-3/+4
| | | | llvm-svn: 137253
* While extending definition range of a debug variable, consult lexical scopes ↵Devang Patel2011-08-101-10/+22
| | | | | | also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases. llvm-svn: 137250
* Revert unintentional parts of previous check-in.Devang Patel2011-08-101-5/+2
| | | | llvm-svn: 137249
* Start using LexicalScopes utility. No intetional functionality change.Devang Patel2011-08-102-526/+113
| | | | llvm-svn: 137246
* Provide utility to extract and use lexical scoping information from machine ↵Devang Patel2011-08-102-0/+306
| | | | | | instructions. llvm-svn: 137237
* Trim an unneeded header.Jakob Stoklund Olesen2011-08-092-0/+2
| | | | llvm-svn: 137184
* Inflate register classes after coalescing.Jakob Stoklund Olesen2011-08-091-2/+35
| | | | | | | | | | | | | | | | | | | | | | | Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. llvm-svn: 137133
* Move CalculateRegClass to MRI::recomputeRegClass.Jakob Stoklund Olesen2011-08-093-34/+36
| | | | | | | | This function doesn't have anything to do with spill weights, and MRI already has functions for manipulating the register class of a virtual register. llvm-svn: 137123
* Print variable's inline location in debug output.Devang Patel2011-08-091-2/+5
| | | | llvm-svn: 137096
* Rename member variables to follow coding standards.Jakob Stoklund Olesen2011-08-092-231/+232
| | | | | | No functional change. llvm-svn: 137094
* Move the RegisterCoalescer private to its implementation file.Jakob Stoklund Olesen2011-08-092-142/+123
| | | | | | RegisterCoalescer.h still has the CoalescerPair class interface. llvm-svn: 137088
* Refer to the RegisterCoalescer pass by ID.Jakob Stoklund Olesen2011-08-096-13/+8
| | | | | | | A public interface is no longer needed since RegisterCoalescer is not an analysis any more. llvm-svn: 137082
* Hoist hasLoadFromStackSlot and hasStoreToStackSlot.Jakob Stoklund Olesen2011-08-081-0/+36
| | | | | | | These the methods are target-independent since they simply scan the memory operands. They can live in TargetInstrInfoImpl. llvm-svn: 137063
* Simplify by creating parent first.Devang Patel2011-08-081-19/+14
| | | | llvm-svn: 137056
* Fix typo. Thanks, Andy!Jakob Stoklund Olesen2011-08-061-1/+1
| | | | llvm-svn: 137023
* Reject RS_Spill ranges from local splitting as well.Jakob Stoklund Olesen2011-08-051-4/+4
| | | | | | | All new local ranges are marked as RS_New now, so there is no need to attempt splitting of RS_Spill ranges any more. llvm-svn: 137002
* Only mark remainder intervals as RS_Spill after per-block splitting.Jakob Stoklund Olesen2011-08-051-2/+12
| | | | | | | | | | The local ranges created get to stay in the RS_New stage, just like for local and region splitting. This gives tryLocalSplit a bit more freedom the first time it sees one of these new local ranges. llvm-svn: 137001
* Remember to update LiveDebugVariables after per-block splitting.Jakob Stoklund Olesen2011-08-051-1/+5
| | | | llvm-svn: 136996
* Extract per-block splitting into its own method.Jakob Stoklund Olesen2011-08-051-23/+36
| | | | | | No functional change. llvm-svn: 136994
* Delete getMultiUseBlocks and splitSingleBlocks.Jakob Stoklund Olesen2011-08-052-38/+0
| | | | | | | These functions are no longer used, and they are easily replaced with a loop calling shouldSplitSingleBlock and splitSingleBlock. llvm-svn: 136993
* Also use shouldSplitSingleBlock() in the fallback splitting mode.Jakob Stoklund Olesen2011-08-051-8/+18
| | | | | | | Drop the use of SplitAnalysis::getMultiUseBlocks, there is no need to go through a SmallPtrSet any more. llvm-svn: 136992
* Split around single instructions to enable register class inflation.Jakob Stoklund Olesen2011-08-053-1/+35
| | | | | | | | | | | | | Normally, we don't create a live range for a single instruction in a basic block, the spiller does that anyway. However, when splitting a live range that belongs to a proper register sub-class, inserting these extra COPY instructions completely remove the constraints from the remainder interval, and it may be allocated from the larger super-class. The spiller will mop up these small live ranges if we end up spilling anyway. It calls them snippets. llvm-svn: 136989
* Detect proper register sub-classes.Jakob Stoklund Olesen2011-08-052-2/+18
| | | | | | | | | | | | | | | | | Some instructions require restricted register classes, but most of the time that doesn't affect register allocation. For example, some instructions don't work with the stack pointer, but that is a reserved register anyway. Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For such a proper sub-class, the register allocator should try to enable register class inflation since that makes more registers available for allocation. Make sure only legal super-classes are considered. For example, tGPR is not a proper sub-class in Thumb mode, but in ARM mode it is. llvm-svn: 136981
* Fix liveness computations in BranchFolding.Jakob Stoklund Olesen2011-08-051-13/+16
| | | | | | | | | | | | | | | | | | | | | | | The old code would look at kills and defs in one pass over the instruction operands, causing problems with this code: %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg The last instruction kills and redefines %R0, so it is still live after the instruction. This caused a register scavenger crash when compiling 483.xalancbmk for armv6. I am not including a test case because it requires too much bad luck to expose this old bug. First you need to convince the register allocator to use %R0 twice on the tADDrr instruction, then you have to convince BranchFolding to do something that causes it to run the register scavenger on he bad block. <rdar://problem/9898200> llvm-svn: 136973
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