Fix PR 10635. When generating integer constants, the constant element type may

be illegal, even if the requested vector type is legal. Testcase is one of the
disabled ARM tests in the vector-select patch.

llvm-svn: 137562

1 files changed, 7 insertions, 0 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 8b353a28b6b..ab6af1b4d17 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -928,6 +928,13 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) {
   assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
          "APInt size does not match type size!");
 
+  // In some cases the vector type is legal but the element type is illegal.
+  // In this case, promote the inserted value. The type does not need to match
+  // the vector element type. Any extra bits introduced will be
+  // truncated away.
+  if (VT.isVector())
+    EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
+
   unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);