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* Re-commit 127368 and 127371. They are exonerated.Evan Cheng2011-03-102-10/+23
| | | | llvm-svn: 127380
* Revert 127368 and 127371 for now.Evan Cheng2011-03-092-23/+10
| | | | llvm-svn: 127376
* Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng2011-03-092-10/+23
| | | | | | | | | | | | | flexible. If it returns a register class that's different from the input, then that's the register class used for cross-register class copies. If it returns a register class that's the same as the input, then no cross- register class copies are needed (normal copies would do). If it returns null, then it's not at all possible to copy registers of the specified register class. llvm-svn: 127368
* Make physreg coalescing independent on the number of uses of the virtual ↵Jakob Stoklund Olesen2011-03-091-3/+1
| | | | | | | | | | | | | | | | | register. The damage done by physreg coalescing only depends on the number of instructions the extended physreg live range covers. This fixes PR9438. The heuristic is still luck-based, and physreg coalescing really should be disabled completely. We need a register allocator with better hinting support before that is possible. Convert a test to FileCheck and force spilling by inserting an extra call. The previous spilling behavior was dependent on misguided physreg coalescing decisions. llvm-svn: 127351
* Improve pre-RA-sched register pressure tracking for duplicate operands.Andrew Trick2011-03-091-1/+5
| | | | | | This helps cases like 2008-07-19-movups-spills.ll, but doesn't have an obvious impact on benchmarks llvm-svn: 127347
* Fix typo, make helper static.Benjamin Kramer2011-03-091-3/+3
| | | | llvm-svn: 127335
* Remove unused virtual dtor.Benjamin Kramer2011-03-091-1/+0
| | | | llvm-svn: 127331
* Add a virtual dtor to Delegate to silence -Wnon-virtual-dtorMatt Beaumont-Gay2011-03-091-0/+1
| | | | llvm-svn: 127311
* Add a LiveRangeEdit::Delegate protocol.Jakob Stoklund Olesen2011-03-094-7/+38
| | | | | | | This will we used for keeping register allocator data structures up to date while LiveRangeEdit is trimming live intervals. llvm-svn: 127300
* Delete dead code.Jakob Stoklund Olesen2011-03-091-10/+0
| | | | llvm-svn: 127295
* Delete dead code after rematerializing.Jakob Stoklund Olesen2011-03-084-1/+107
| | | | | | | | LiveRangeEdit::eliminateDeadDefs() will eventually be used by coalescing, splitting, and spilling for dead code elimination. It can delete chains of dead instructions as long as there are no dependency loops. llvm-svn: 127287
* Fix the build for MSVC 9 whose upper_bound() wants to compare elements in ↵Jakob Stoklund Olesen2011-03-081-0/+3
| | | | | | | | the sorted array. Patch by Olaf Krzikalla! llvm-svn: 127264
* Fix some latent bugs if the nodes are unschedulable. We'd gotten awayEric Christopher2011-03-082-1/+10
| | | | | | | | | | | | with this before since none of the register tracking or nightly tests had unschedulable nodes. This should probably be refixed with a special default Node that just returns some "don't touch me" values. Fixes PR9427 llvm-svn: 127263
* Revert "Make a comparator's argument `const'. This fixes the build forOscar Fuentes2011-03-081-1/+1
| | | | | | | | | | MSVC 9." The "fix" was meaningless. This reverts commit r127245. llvm-svn: 127260
* Reduce vector reallocations.Benjamin Kramer2011-03-081-4/+2
| | | | llvm-svn: 127254
* Make a comparator's argument `const'. This fixes the build for MSVC 9.Oscar Fuentes2011-03-081-1/+1
| | | | llvm-svn: 127245
* Further improvements to pre-RA-sched=list-ilp.Andrew Trick2011-03-081-17/+62
| | | | | | | This change uses the MaxReorderWindow for both height and depth, which tends to limit the negative effects of high register pressure. llvm-svn: 127203
* Let shrinkToUses optionally return a list of now dead machine instructions.Jakob Stoklund Olesen2011-03-071-1/+6
| | | | llvm-svn: 127192
* Make the UselessRegs argument optional in the LiveRangeEdit constructor.Jakob Stoklund Olesen2011-03-074-13/+11
| | | | llvm-svn: 127181
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-072-2/+2
| | | | llvm-svn: 127175
* Handle the special case of registers begin redefined by early-clobber defs.Jakob Stoklund Olesen2011-03-071-0/+7
| | | | | | | In this case, the value need to be available at the load index instead of the normal use index. llvm-svn: 127167
* Use the correct LHS type when determining the legalization of a shift's RHS ↵Owen Anderson2011-03-072-5/+8
| | | | | | type. llvm-svn: 127163
* Typo.Eric Christopher2011-03-061-1/+1
| | | | llvm-svn: 127131
* lib/CodeGen/AsmPrinter/CMakeLists.txt: Fix CMake build, following up to r127099.NAKAMURA Takumi2011-03-061-0/+1
| | | | llvm-svn: 127114
* Disable a couple of experimental heuristics to get the best results from the ↵Andrew Trick2011-03-061-2/+2
| | | | | | current implementation of -pre-RA-sched=list-ilp. llvm-svn: 127113
* Some first rudimentary support for ARM EHABI: print exception table in "text ↵Anton Korobeynikov2011-03-054-0/+123
| | | | | | mode". llvm-svn: 127099
* Add FrameSetup MI flagsAnton Korobeynikov2011-03-051-10/+23
| | | | llvm-svn: 127098
* Work around a coalescer bug.Jakob Stoklund Olesen2011-03-052-4/+23
| | | | | | | | | | | | The coalescer can in very rare cases leave too large live intervals around after rematerializing cheap-as-a-move instructions. Linear scan doesn't really care, but live range splitting gets very confused when a live range is killed by a ghost instruction. I will fix this properly in the coalescer after 2.9 branches. llvm-svn: 127096
* Be explicit with abs(). Visual Studio workaround.Andrew Trick2011-03-051-4/+6
| | | | llvm-svn: 127075
* Fix for -sched-high-latency-cycles in sched=list-ilp mode.Andrew Trick2011-03-051-1/+3
| | | | llvm-svn: 127071
* Missing comment.Andrew Trick2011-03-051-0/+2
| | | | llvm-svn: 127068
* Increased the register pressure limit on x86_64 from 8 to 12Andrew Trick2011-03-052-23/+156
| | | | | | | | | | | | | | | | | | | | | | | regs. This is the only change in this checkin that may affects the default scheduler. With better register tracking and heuristics, it doesn't make sense to artificially lower the register limit so much. Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to give the scheduler a way to account for div and sqrt on targets that don't have an itinerary. It is currently defaults to 10 (the actual number doesn't matter much), but only takes effect on non-default schedulers: list-hybrid and list-ilp. Added several heuristics that can be individually disabled for the non-default sched=list-ilp mode. This helps us determine how much better we can do on a given benchmark than the default scheduler. Certain compute intensive loops run much faster in this mode with the right set of heuristics, and it doesn't seem to have much negative impact elsewhere. Not all of the heuristics are needed, but we still need to experiment to decide which should be disabled by default for sched=list-ilp. llvm-svn: 127067
* Rework the global split cost calculation.Jakob Stoklund Olesen2011-03-051-21/+30
| | | | | | | The global cost is the sum of block frequencies for spill code that must be inserted because preferences weren't met. llvm-svn: 127062
* Compute the constraints for global live range splitting from an interference ↵Jakob Stoklund Olesen2011-03-051-163/+67
| | | | | | | | | | | pattern. This simplifies the code and makes it faster too. The interference patterns are saved for each candidate register. It will be reused for actually executing the split. Work in progress. llvm-svn: 127054
* Teach the register scavenger to take subregs into account when finding a ↵Jim Grosbach2011-03-051-5/+10
| | | | | | free register. llvm-svn: 127049
* Improve readability with some whitespace!Eric Christopher2011-03-041-1/+1
| | | | llvm-svn: 127043
* Extract a method. No functional change.Jakob Stoklund Olesen2011-03-041-40/+52
| | | | llvm-svn: 127040
* Go back to comparing spill weights when deciding if interference can be evicted.Jakob Stoklund Olesen2011-03-041-9/+5
| | | | | | | It gives better results. Sometimes, a live range can be large and still have high spill weight. Such a range should not be spilled. llvm-svn: 127036
* Renumber slot indexes locally when possible.Jakob Stoklund Olesen2011-03-041-2/+25
| | | | | | | | | | | | | Initially, slot indexes are quad-spaced. There is room for inserting up to 3 new instructions between the original instructions. When we run out of indexes between two instructions, renumber locally using double-spaced indexes. The original quad-spacing means that we catch up quickly, and we only have to renumber a handful of instructions to get a monotonic sequence. This is much faster than renumbering the whole function as we did before. llvm-svn: 127023
* Number SlotIndexes uniformly without looking at the number of defs on each ↵Jakob Stoklund Olesen2011-03-041-24/+5
| | | | | | | | | | | | instruction. You can't really predict how many indexes will be needed from the number of defs, so let's keep it simple. Also remove an extra empty index that was inserted after each basic block. It was intended for live-out ranges, but it was never used that way. llvm-svn: 127014
* Add SlotIndex statistics.Jakob Stoklund Olesen2011-03-041-0/+4
| | | | llvm-svn: 127007
* Tweak debug output. No functional changes.Jakob Stoklund Olesen2011-03-042-10/+6
| | | | llvm-svn: 127006
* Revert commit 126684 "Use the correct shift amount type". It is only the ↵Duncan Sands2011-03-041-1/+1
| | | | | | | | | | | correct type after type legalization has completed. Before then it may simply not be big enough to hold the shift amount, particularly on x86 which uses a very small type for shifts (this issue broke stuff in the past which is why LegalizeTypes carefully uses a large type for shift amounts). llvm-svn: 127000
* Minor pre-RA-sched fixes and cleanup.Andrew Trick2011-03-041-7/+15
| | | | | | | | Fix the PendingQueue, then disable it because it's not required for the current schedulers' heuristics. Fix the logic for the unused list-ilp scheduler. llvm-svn: 126981
* Precompute block frequencies, pow() isn't free.Jakob Stoklund Olesen2011-03-043-17/+15
| | | | llvm-svn: 126975
* Use an IndexedMap instead of a DenseMap for the live-out cache.Jakob Stoklund Olesen2011-03-042-48/+47
| | | | | | | This speeds up updateSSA() so it only accounts for 5% of the live range splitting time. llvm-svn: 126972
* There are times when the landing pad won't have a call to 'eh.selector' inBill Wendling2011-03-031-9/+23
| | | | | | | | | | | | | | it. It's been assumed up til now that it would be in its immediate successor. However, this isn't necessarily the case. It could be in one of its successor's successors. Modify the code to more thoroughly check for an 'eh.selector' call in successors. It only looks at a successor if we get there as a result of an unconditional branch. Testcase ObjC/exceptions-4.m in r126968. llvm-svn: 126969
* Revert r123908; the code in question is completely untested and wrong.Eli Friedman2011-03-032-28/+0
| | | | llvm-svn: 126964
* Fix typo.Devang Patel2011-03-031-1/+1
| | | | llvm-svn: 126962
* Fix thinko in previous check-in.Devang Patel2011-03-031-1/+3
| | | | | | Add comment. llvm-svn: 126959
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