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authorJakob Stoklund Olesen <stoklund@2pi.dk>2011-03-09 19:27:06 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2011-03-09 19:27:06 +0000
commitd0db705256b616b6fa89bb8c0827d06d73d0ce44 (patch)
tree338fb69e8eb901a42328174c89761d5baec73e46 /llvm/lib/CodeGen
parent456e104c13cb1041582cfe68cd242dd72d27bded (diff)
downloadbcm5719-llvm-d0db705256b616b6fa89bb8c0827d06d73d0ce44.tar.gz
bcm5719-llvm-d0db705256b616b6fa89bb8c0827d06d73d0ce44.zip
Make physreg coalescing independent on the number of uses of the virtual register.
The damage done by physreg coalescing only depends on the number of instructions the extended physreg live range covers. This fixes PR9438. The heuristic is still luck-based, and physreg coalescing really should be disabled completely. We need a register allocator with better hinting support before that is possible. Convert a test to FileCheck and force spilling by inserting an extra call. The previous spilling behavior was dependent on misguided physreg coalescing decisions. llvm-svn: 127351
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp4
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 74898c210a4..8a102702ef3 100644
--- a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1038,9 +1038,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
- if (Length > Threshold &&
- std::distance(mri_->use_nodbg_begin(CP.getSrcReg()),
- mri_->use_nodbg_end()) * Threshold < Length) {
+ if (Length > Threshold) {
// Before giving up coalescing, if definition of source is defined by
// trivial computation, try rematerializing it.
if (!CP.isFlipped() &&
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