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A local live range is live in a single basic block. If such a range fails to
allocate, try to find a sub-range that would get a larger spill weight than its
interference.
llvm-svn: 125764
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the time but presumably my email got lost). Examples where the previous logic
got it wrong: (1) a signed i8 multiply of 64 by 2 overflows, but the high part is
zero; (2) a signed i8 multiple of -128 by 2 overflows, but the high part is all
ones.
llvm-svn: 125748
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llvm-svn: 125728
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llvm-svn: 125727
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llvm-svn: 125726
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other getNode() methods. Radar 9002173.
llvm-svn: 125665
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llvm-svn: 125651
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transformation if we can't legally create a build vector of the correct
type. Check that we can make the transformation first, and add a TODO to
refactor this code with similar cases.
Fixes: PR9223 and rdar://9000350
llvm-svn: 125631
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llvm-svn: 125625
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based on location info.
Machine instruction range consisting of only DBG_VALUE MIs only contributes consecutive labels in assembly output, which is harmless, and empty scope entry in DebugInfo, which confuses debugger tools.
llvm-svn: 125577
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llvm-svn: 125563
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llvm-svn: 125552
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llvm-svn: 125537
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Simplify the spill weight calculation a bit by bypassing
getApproximateInstructionCount() and using LiveInterval::getSize() directly.
This changes the computed spill weights, but only by a constant factor in each
function. It should not affect how spill weights compare against each other, and
so it shouldn't affect code generation.
llvm-svn: 125530
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section.
llvm-svn: 125526
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hard to reduce a sensible small test case.
llvm-svn: 125523
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builders unhappy.
llvm-svn: 125504
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llvm-svn: 125490
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idiom. Change various clients to simplify their code.
llvm-svn: 125487
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vector fp conversions.
llvm-svn: 125482
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llvm-svn: 125481
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llvm-svn: 125477
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llvm-svn: 125476
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have their low bits set to zero. This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.
Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively. Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST). The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.
llvm-svn: 125470
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generating i8 shift amounts for things like i1024 types. Add
an assert in getNode to prevent this from occuring in the future,
fix the buggy transformation, revert my previous patch, and
document this gotcha in ISDOpcodes.h
llvm-svn: 125465
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the shift amounts are in a suitably wide type so that
we don't generate out of range constant shift amounts.
This fixes PR9028.
llvm-svn: 125458
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is narrower than the shift register. Doing an anyext provides undefined bits in
the top part of the register.
llvm-svn: 125457
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The DAGCombiner created illegal BUILD_VECTOR operations.
The patch added a check that either illegal operations are
allowed or that the created operation is legal.
llvm-svn: 125435
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that the condition is not a vector.
llvm-svn: 125398
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The bug happens when the DAGCombiner attempts to optimize one of the patterns
of the SUB opcode. It tries to create a zero of type v2i64. This type is legal
on 32bit machines, but the initializer of this vector (i64) is target dependent.
Currently, the initializer attempts to create an i64 zero constant, which fails.
Added a flag to tell the DAGCombiner to create a legal zero, if we require that
the pass would generate legal types.
llvm-svn: 125391
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add a missing check when considering whether it's profitable to commute. rdar://8977508.
llvm-svn: 125259
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Loop splitting is better handled by the more generic global region splitting
based on the edge bundle graph.
llvm-svn: 125243
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llvm-svn: 125238
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This fixes a bug where splitSingleBlocks() could split a live range after a
terminator instruction.
llvm-svn: 125237
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llvm-svn: 125232
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No functional changes intended.
llvm-svn: 125231
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llvm-svn: 125226
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llvm-svn: 125225
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The tag is updated whenever the live interval union is changed, and it is tested
before using cached information.
llvm-svn: 125224
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Registers are not allocated strictly in spill weight order when live range
splitting and spilling has created new shorter intervals with higher spill
weights.
When one of the new heavy intervals conflicts with a single lighter interval,
simply evict the old interval instead of trying to split the heavy one.
The lighter interval is a better candidate for splitting, it has a smaller use
density.
llvm-svn: 125151
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This almost guarantees that the COPY will be coalesced.
llvm-svn: 125140
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llvm-svn: 125137
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The last split point can be anywhere in the block, so it interferes with the
strictly monotonic requirements of advanceTo().
llvm-svn: 125132
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instruction in a basic block.
llvm-svn: 125116
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allocation.
This is a lot easier than trying to get kill flags right during live range
splitting and rematerialization.
llvm-svn: 125113
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llvm-svn: 125109
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register.
The target hook doesn't know how to do that. (Neither do I).
llvm-svn: 125108
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are live.
If a live range is used by a terminator instruction, and that live range needs
to leave the block on the stack or in a different register, it can be necessary
to have both sides of the split live at the terminator instruction.
Example:
%vreg2 = COPY %vreg1
JMP %vreg1
Becomes after spilling %vreg2:
SPILL %vreg1
JMP %vreg1
The spill doesn't kill the register as is normally the case.
llvm-svn: 125102
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llvm-svn: 125101
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Avoid using the same register for two def operands or and earlyclobber
def and use operand. This fixes PR8986 and improves on the prior fix
for rdar://problem/8959122.
llvm-svn: 125089
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