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* Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper2012-01-071-4/+4
| | | | llvm-svn: 147733
* Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper2012-01-071-2/+51
| | | | | | subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. llvm-svn: 147728
* Optimize reserved register coalescing.Jakob Stoklund Olesen2012-01-071-0/+25
| | | | | | | | | | | | | | | | | Reserved registers don't have proper live ranges, their LiveInterval simply has a snippet of liveness for each def. Virtual registers with a single value that is a copy of a reserved register (typically %esp) can be coalesced with the reserved register if the live range doesn't overlap any reserved register defs. When coalescing with a reserved register, don't modify the reserved register live range. Just leave it as a bunch of dead defs. This eliminates quadratic coalescer behavior in i386 functions with many function calls. PR11699 llvm-svn: 147726
* Use the 'regalloc' debug tag for most register allocator tracing.Jakob Stoklund Olesen2012-01-073-3/+3
| | | | llvm-svn: 147725
* Revert part of r147716. Looks like x87 instructions kill markers are all messedEvan Cheng2012-01-071-9/+11
| | | | | | | | | | up so branch folding pass can't use the scavenger. :-( This doesn't breaks anything currently. It just means targets which do not carefully update kill markers cannot run post-ra scheduler (not new, it has always been the case). We should fix this at some point since it's really hacky. llvm-svn: 147719
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-079-38/+274
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Missing raw_ostream.h breaks MSVC build.Andrew Trick2012-01-071-0/+1
| | | | llvm-svn: 147703
* Add comment.Chad Rosier2012-01-061-0/+4
| | | | llvm-svn: 147696
* Add a comment and ensure that anyone else looking at this code doesn't startEric Christopher2012-01-061-6/+5
| | | | | | to bleed from the eyes. llvm-svn: 147695
* Use const vector references instead of a vector copy. Spotted by Devang.Eric Christopher2012-01-061-4/+4
| | | | llvm-svn: 147694
* Use -> instead of (*iter).Eric Christopher2012-01-061-10/+10
| | | | llvm-svn: 147693
* Tracing to help investigate issues with SjLj spill code.Andrew Trick2012-01-061-0/+2
| | | | llvm-svn: 147682
* Fix a leak I noticed while reviewing the accelerator table changes. PassesEric Christopher2012-01-061-0/+5
| | | | | | | | lldb testsuite. rdar://10652330 llvm-svn: 147673
* As part of the ongoing work in finalizing the accelerator tables, extendEric Christopher2012-01-065-38/+110
| | | | | | | | | the debug type accelerator tables to contain the tag and a flag stating whether or not a compound type is a complete type. rdar://10652330 llvm-svn: 147651
* Kill ObjectCodeEmitter and BinaryObject, they were unused and superseded by MC.Benjamin Kramer2012-01-052-142/+0
| | | | llvm-svn: 147618
* Remove the old ELF writer.Rafael Espindola2012-01-056-1868/+0
| | | | llvm-svn: 147615
* Remove an unused variable.Chandler Carruth2012-01-051-1/+0
| | | | llvm-svn: 147605
* Prevent a DAGCombine from firing where there are two uses ofChandler Carruth2012-01-051-1/+3
| | | | | | | | | a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. llvm-svn: 147604
* Minor postra scheduler cleanup. It could result in more precise ↵Andrew Trick2012-01-051-25/+19
| | | | | | antidependence latency on ARM in exceedingly rare cases. llvm-svn: 147594
* Freeze reserved registers before starting register allocation.Jakob Stoklund Olesen2012-01-054-0/+7
| | | | | | | | | | | The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. llvm-svn: 147577
* Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper2012-01-041-11/+24
| | | | | | are commuted in the shuffle mask. llvm-svn: 147527
* Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper2012-01-041-2/+50
| | | | llvm-svn: 147525
* Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner2012-01-031-9/+21
| | | | | | | | | | | | | | | | | | Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. llvm-svn: 147502
* Assert when reserved registers have been assigned.Jakob Stoklund Olesen2012-01-031-0/+4
| | | | | | | | | This can only happen if the set of reserved registers changes during register allocation. <rdar://problem/10625436> llvm-svn: 147486
* Fix incorrect widening of the bitcast sdnode in case the incoming operand is ↵Nadav Rotem2012-01-031-0/+6
| | | | | | integer-promoted. llvm-svn: 147484
* Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson2012-01-031-8/+0
| | | | | | Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
* Clarified assert text.Lang Hames2012-01-031-1/+1
| | | | llvm-svn: 147471
* Fix typo in ruler. No functionality change.Nick Lewycky2012-01-031-1/+1
| | | | llvm-svn: 147454
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-031-6/+50
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147445
* Revert 147399. It broke CodeGen/ARM/vext.ll.Rafael Espindola2012-01-011-39/+5
| | | | llvm-svn: 147400
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-011-5/+39
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147399
* PR11662.Nadav Rotem2011-12-281-1/+5
| | | | | | Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. llvm-svn: 147309
* Make sure DAGCombiner doesn't introduce multiple loads from the same memory ↵Eli Friedman2011-12-261-1/+23
| | | | | | location. PR10747, part 2. llvm-svn: 147283
* Fix a typo in the widening of vectors in PromoteIntRes. Patch by Shemer Anat.Nadav Rotem2011-12-251-2/+2
| | | | llvm-svn: 147272
* drop unneeded config.h includesDylan Noblesmith2011-12-223-3/+0
| | | | llvm-svn: 147197
* Hoisted some loop invariant smallvector lookups out of a MachineLICM loopPete Cooper2011-12-221-1/+3
| | | | llvm-svn: 147127
* Changed MachineLICM to use a worklist list MachineCSE instead of recursion.Pete Cooper2011-12-221-44/+125
| | | | | | Fixes <rdar://problem/10584116> llvm-svn: 147125
* Revert patch from 147090. There is not point to make code less readable if weJakub Staszak2011-12-211-43/+45
| | | | | | don't get any serious benefit there. llvm-svn: 147101
* - Change a few operator[] to lookup which is cheaper.Jakub Staszak2011-12-211-45/+43
| | | | | | - Add some constantness. llvm-svn: 147090
* Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header ↵Lang Hames2011-12-211-0/+2
| | | | | | include to LiveIntervalUnion.cpp file. llvm-svn: 147089
* Remove disused STL header include.Lang Hames2011-12-211-2/+0
| | | | llvm-svn: 147088
* Move common code into an MRI function.Jakob Stoklund Olesen2011-12-212-14/+5
| | | | llvm-svn: 147071
* Fix assert condition.Lang Hames2011-12-201-1/+1
| | | | llvm-svn: 146987
* Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.Jakub Staszak2011-12-205-9/+20
| | | | llvm-svn: 146986
* Fix up the CMake build for the new files added in r146960, they'reChandler Carruth2011-12-201-0/+2
| | | | | | likely to stay either way that discussion ends up resolving itself. llvm-svn: 146966
* Unweaken vtables as per ↵David Blaikie2011-12-2014-1/+49
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Add basic generic CodeGen support for half.Dan Gohman2011-12-202-17/+39
| | | | llvm-svn: 146927
* Add a if-conversion optimization that allows 'true' side of a diamond to beEvan Cheng2011-12-191-5/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 llvm-svn: 146914
* Attempt to fix PR11607 by shuffling around which class defines which methods.Eli Friedman2011-12-191-5/+5
| | | | llvm-svn: 146897
* Handle sub-register operands in recomputeRegClass().Jakob Stoklund Olesen2011-12-191-4/+6
| | | | | | | | | | | Now that getMatchingSuperRegClass() returns accurate results, it can be used to compute constraints imposed by instructions using a sub-register of a virtual register. This means we can recompute the register class of any virtual register by combining the constraints from all its uses. llvm-svn: 146874
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