summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Minor cleanup; fixes review comments for a previous patch. Sorry for Eli Friedman2009-06-191-4/+3
| | | | | | taking so long to get to this! llvm-svn: 73757
* More VNInfo tweaking, plus a little progress on intra-block splitting.Lang Hames2009-06-193-25/+84
| | | | llvm-svn: 73750
* move mangler quote handling from asm printers to TargetAsmInfo.Chris Lattner2009-06-181-0/+3
| | | | llvm-svn: 73738
* simplify macro debug info directive handling.Chris Lattner2009-06-181-4/+4
| | | | llvm-svn: 73736
* Improved PHI def marking, replaced some gotos with breaks.Lang Hames2009-06-181-5/+7
| | | | llvm-svn: 73727
* On Darwin, ams printer should output a second label before a jump table so ↵Evan Cheng2009-06-181-3/+7
| | | | | | the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body. llvm-svn: 73720
* - Update register allocation hint after coalescing. This is done by the ↵Evan Cheng2009-06-182-2/+11
| | | | | | | | | target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. llvm-svn: 73671
* VNInfo cleanup.Lang Hames2009-06-179-125/+151
| | | | llvm-svn: 73634
* Fixed names of libcalls checked in r73480.Sanjiv Gupta2009-06-161-8/+4
| | | | llvm-svn: 73483
* Added required libcalls for PIC16 (mostly floating points to integer casting ↵Sanjiv Gupta2009-06-161-0/+16
| | | | | | operations). llvm-svn: 73480
* Rename RemoveCopiesFromValNo to TurnCopiesFromValNoToImpDefs.Evan Cheng2009-06-162-10/+10
| | | | llvm-svn: 73479
* If a val# is defined by an implicit_def and it is being removed, all of the ↵Evan Cheng2009-06-161-20/+27
| | | | | | | | copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block. llvm-svn: 73478
* Add some generic expansion logic for SMULO and UMULO. Fixes UMULO Eli Friedman2009-06-161-0/+47
| | | | | | | | support for x86, and UMULO/SMULO for many architectures, including PPC (PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's not bad. llvm-svn: 73477
* Fix typos.Bill Wendling2009-06-161-2/+2
| | | | llvm-svn: 73464
* Use MainCU if it is available.Devang Patel2009-06-161-2/+3
| | | | llvm-svn: 73457
* Owen Anderson 2009-06-15: Use a SmallPtrSet here, for speed and to match ↵Owen Anderson2009-06-151-5/+14
| | | | | | | | df_iterator. Owen Anderson 2009-06-15: Remember to clear out our maps to prevent crashing. llvm-svn: 73438
* Change this from an assert to a cerr+exit, since it's diagnosing anDan Gohman2009-06-151-2/+6
| | | | | | unsupported inline asm construct, rather than verifying a code invariant. llvm-svn: 73435
* Gracefully handle imbalanced inline function begin and end markers.Devang Patel2009-06-152-2/+9
| | | | llvm-svn: 73426
* ifcvt should ignore cfg where true and false successors are the same.Evan Cheng2009-06-151-1/+12
| | | | llvm-svn: 73423
* CheckTailCallReturnConstraints is missing a check on theArnold Schwaighofer2009-06-151-1/+5
| | | | | | | | | incomming chain of the RETURN node. The incomming chain must be the outgoing chain of the CALL node. This causes the backend to identify tail calls that are not tail calls. This patch fixes this. llvm-svn: 73387
* Part 1.Evan Cheng2009-06-155-86/+39
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Fix old-style type names in comments.Dan Gohman2009-06-141-1/+1
| | | | llvm-svn: 73362
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-148-37/+142
| | | | | | MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
* Introduce new BinaryObject (blob) class, ELF Writer modified to use it. ↵Bruno Cardoso Lopes2009-06-144-257/+182
| | | | | | BinaryObject.h by Aaron Gray llvm-svn: 73333
* Add a ARM specific pre-allocation pass that re-schedule loads / stores fromEvan Cheng2009-06-131-1/+1
| | | | | | | | | | | consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. llvm-svn: 73291
* llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block ↵Devang Patel2009-06-131-1/+5
| | | | | | | | in a function. If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available. LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics. Apply defensive patch to preserve at least one lexical scope till the end of function. llvm-svn: 73282
* Improve style.Owen Anderson2009-06-121-16/+16
| | | | llvm-svn: 73258
* This is supposed to be a preorder numbering of the dominator tree, not the CFG.Owen Anderson2009-06-121-4/+5
| | | | llvm-svn: 73257
* Now with less iterator invalidation, and other forms of crashing!Owen Anderson2009-06-121-3/+6
| | | | llvm-svn: 73256
* If killed register is defined by implicit_def, do not clear it since it's ↵Evan Cheng2009-06-121-5/+12
| | | | | | live range may overlap another def of same register. llvm-svn: 73255
* Clear AbstractInstanceRootMap at the end of the function.Devang Patel2009-06-121-0/+1
| | | | llvm-svn: 73244
* Support for ELF VisibilityBruno Cardoso Lopes2009-06-114-93/+295
| | | | | | | | Emission for globals, using the correct data sections Function alignment can be computed for each target using TargetELFWriterInfo Some small fixes llvm-svn: 73201
* CMake: Updated list of files on lib/CodeGen/CMakeLists.txt.Oscar Fuentes2009-06-101-0/+1
| | | | llvm-svn: 73174
* Remove warnings: no newline at end of file.Sanjiv Gupta2009-06-101-1/+2
| | | | llvm-svn: 73156
* Add the beginnings of an implementatation of lazy liveness analysis, based ↵Owen Anderson2009-06-091-0/+153
| | | | | | | | on "Fast Liveness Checking for SSA-form Programs" by Boissinot, et al. This is still very early, hasn't been tested, and is not yet well documented. More to come soon. llvm-svn: 73141
* Delete comment and fix typoBruno Cardoso Lopes2009-06-072-2/+1
| | | | llvm-svn: 73040
* Fix wrong elf class and byte order initializations.Bruno Cardoso Lopes2009-06-071-2/+2
| | | | llvm-svn: 73039
* Simple ELF32/64 binary files can now be emitted for x86 and x86_64 withoutBruno Cardoso Lopes2009-06-075-59/+162
| | | | | | relocation sections. llvm-svn: 73038
* Tweak the expansion code for BIT_CONVERT to generate better code Eli Friedman2009-06-071-0/+20
| | | | | | converting from an MMX vector to an i64. llvm-svn: 73024
* Slightly generalize the code that handles shuffles of consecutive loads Eli Friedman2009-06-071-78/+37
| | | | | | | | | | | on x86 to handle more cases. Fix a bug in said code that would cause it to read past the end of an object. Rewrite the code in SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. Remove PerformBuildVectorCombine, which is no longer necessary with these changes. In addition to simplifying the code, with this change, we can now catch a few more cases of consecutive loads. llvm-svn: 73012
* Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal Eli Friedman2009-06-061-17/+1
| | | | | | types. llvm-svn: 72993
* Factor out a couple of helpers.Eli Friedman2009-06-061-78/+101
| | | | llvm-svn: 72992
* Remove elf specific info from ELFWriter.h to Elf.h. Code cleanup and more ↵Bruno Cardoso Lopes2009-06-065-116/+245
| | | | | | comments added llvm-svn: 72982
* Make SINT_TO_FP/UINT_TO_FP vector legalization queries query on the Eli Friedman2009-06-061-3/+7
| | | | | | | integer type to be consistent with normal operation legalization. No visible change because nothing is actually using this at the moment. llvm-svn: 72980
* Add new function attribute - noimplicitfloatDevang Patel2009-06-051-1/+1
| | | | | | | Update code generator to use this attribute and remove NoImplicitFloat target option. Update llc to set this attribute when -no-implicit-float command line option is used. llvm-svn: 72959
* Adapt the x86 build_vector dagcombine to the current state of the legalizer.Nate Begeman2009-06-052-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | build vectors with i64 elements will only appear on 32b x86 before legalize. Since vector widening occurs during legalize, and produces i64 build_vector elements, the dag combiner is never run on these before legalize splits them into 32b elements. Teach the build_vector dag combine in x86 back end to recognize consecutive loads producing the low part of the vector. Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes since that was required implicitly. Add a testcase for the transform. Old: subl $28, %esp movl 32(%esp), %eax movl 4(%eax), %ecx movl %ecx, 4(%esp) movl (%eax), %eax movl %eax, (%esp) movaps (%esp), %xmm0 pmovzxwd %xmm0, %xmm0 movl 36(%esp), %eax movaps %xmm0, (%eax) addl $28, %esp ret New: movl 4(%esp), %eax pmovzxwd (%eax), %xmm0 movl 8(%esp), %eax movaps %xmm0, (%eax) ret llvm-svn: 72957
* Remove some unnecessary #includes.Dan Gohman2009-06-053-3/+0
| | | | llvm-svn: 72948
* Allow libcalls for i16 sdiv/udiv/rem operations.Sanjiv Gupta2009-06-051-4/+12
| | | | llvm-svn: 72941
* ELF Code Emitter now uses CurBufferPtr, BufferBegin and BufferEnd, as do JIT andBruno Cardoso Lopes2009-06-053-32/+57
| | | | | | | MachO Writer. This will change with the arrival of ObjectCodeEmitter and BinaryObject llvm-svn: 72906
* Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman2009-06-043-47/+32
| | | | | | | | | | | | | | | integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
OpenPOWER on IntegriCloud