| Commit message (Collapse) | Author | Age | Files | Lines |
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GetDemandBits (which must operate on the vector element type).
Fix the a usage of getZeroExtendInReg which must also be done on scalar types.
llvm-svn: 133052
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converted to add x,x if x is a undef. add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.
llvm-svn: 133022
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llvm-svn: 133007
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Dan noted that this would work on the case shown on the commit message. I think
the case that was failing was a bb ending with a redundant conditional jump:
...
jne foo
foo:
...
I was unable to find any such case in the tests or in a debug build of clang,
so I will revert this part of the patch and watch the bots.
llvm-svn: 133004
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llvm-svn: 132995
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llvm-svn: 132988
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types (with power of two types such as 8,16,32 .. 512).
Fix a bug in the integer promotion of bitcast nodes. Enable integer expanding
only if the target of the conversion is an integer (when the type action is
scalarize).
Add handling to the legalization of vector load/store in cases where the saved
vector is integer-promoted.
llvm-svn: 132985
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llvm-svn: 132984
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AnalyzeBranch.
llvm-svn: 132981
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or instruction cache access. Update the targets to match it and also teach
autoupgrade.
llvm-svn: 132976
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sharp all or nothing transition when one extra predecessor was added. Now
we still test first ones for merging.
llvm-svn: 132974
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only if the number of packed elements is a power of two.
Bug found in Duncan's testcase.
llvm-svn: 132923
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In particular, don't spill dirty registers only to satisfy a hint. It is
not worth it.
The attached test case provides an example where the fast allocator
would spill a register when other registers are available.
llvm-svn: 132900
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llvm-svn: 132899
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having.
llvm-svn: 132898
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types such as i33 were rounded to i32. Originated from Duncan's testcase.
llvm-svn: 132893
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Instead of scalarizing, and doing an element-by-element truncat, use vector
truncate.
Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's
testcase).
llvm-svn: 132892
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Add a triple to the tests.
llvm-svn: 132885
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llvm-svn: 132883
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we try to branch to them.
Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for
-----------
...
jne foo
jmp bar
foo:
----------
llvm-svn: 132882
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llvm-svn: 132872
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llvm-svn: 132871
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llvm-svn: 132863
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llvm-svn: 132857
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comment on their meaning.
llvm-svn: 132854
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llvm-svn: 132853
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llvm-svn: 132852
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Thanks Bob Wilson for noticing it!
llvm-svn: 132851
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and definitions when emitting global variables. This was causing global
declarations to be emitted as if they were definitions.
Fixes <rdar://problem/9429892>.
llvm-svn: 132825
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llvm-svn: 132822
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llvm-svn: 132821
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With this I am able to bootstrap clang with early tail duplication enabled
for any small bb and setting tail-dup-size to a relatively large value(8) to
stress this code.
llvm-svn: 132816
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llvm-svn: 132814
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matches the ordering we prefer in instcombine. Part of rdar://9562809.
The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.
llvm-svn: 132809
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eh edges. Swap the order of the checks to avoid it.
llvm-svn: 132806
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llvm-svn: 132805
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No functionality change.
llvm-svn: 132798
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llvm-svn: 132776
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llvm-svn: 132771
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of the frame then increase the maximum alignment of the frame to
match.
Fixes PR6965
llvm-svn: 132764
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No functional change.
Part of PR6965
llvm-svn: 132763
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llvm-svn: 132751
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llvm-svn: 132749
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llvm-svn: 132748
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operands to an early clobber register. This fixes <rdar://problem/9566076>.
llvm-svn: 132738
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Fixes PR10095.
llvm-svn: 132735
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I've been sitting on this long enough trying to find a test case. I
think the fix should go in now, but I'll keep working on the test case.
llvm-svn: 132701
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When local live range splitting creates a live range with the same
number of instructions as the old range, mark it as RS_Local. When such
a range is seen again, require that it be split in a way that reduces
the number of instructions. That guarantees we are making progress while
still being able to perform 3 -> 2+3 splits as required by PR10070.
This also means that the PrevSlot map is no longer needed. This was also
used to estimate new spill weights, but that is no longer necessary
after slotIndexes::insertMachineInstrInMaps() got the extra Late
insertion argument.
llvm-svn: 132697
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Only target-dependent hints require callbacks. The RCI allocation order
has CSR aliases last according to their order of appearance in the
getCalleeSavedRegs list. This can depend on the calling convention.
This way, AllocationOrder::next doesn't have to check for reserved
registers, and CSRs are always allocated last, even with weird calling
conventions.
llvm-svn: 132690
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legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc.
llvm-svn: 132689
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