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* Fix small grammar-o.Eric Christopher2018-05-161-1/+1
| | | | llvm-svn: 332522
* [DAG] Prune cycle check in store merge.Nirav Dave2018-05-161-18/+54
| | | | | | | | | | | | | | | | | | | | As part of merging stores we check that fusing the nodes does not cause a cycle due to one candidate store being indirectly dependent on another store (this may happen via chained memory copies). This is done by searching if a store is a predecessor to another store's value. Prune the search at the candidate search's root node which is a predecessor to all candidate stores. This reduces the size of the subgraph searched in large basic blocks. Reviewers: jyknight Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D46955 llvm-svn: 332490
* [DAG] Defer merge store cycle checking to just before merge. NFCI.Nirav Dave2018-05-161-8/+20
| | | | llvm-svn: 332489
* [AArch64] Gangup loads and stores for pairing.Sirish Pande2018-05-162-4/+86
| | | | | | | | | | Keep loads and stores together (target defines how many loads and stores to gang up), such that it will help in pairing and vectorization. Differential Revision https://reviews.llvm.org/D46477 llvm-svn: 332482
* [GlobalISel][IRTranslator] Split aggregates during IR translation.Amara Emerson2018-05-161-135/+280
| | | | | | | | | | | | | | | | | | | | | We currently handle all aggregates by creating one large LLT, and letting the legalizer deal with splitting them up. However using this approach means that we can't support big endian code correctly. This patch changes the way that the IRTranslator deals with aggregate values, by splitting them up into their constituent element values. To do this, parts of the translator need to be modified to deal with multiple VRegs for a single Value. A new Value to VReg mapper is introduced to help keep compile time under control, currently there is no measurable impact on CTMark despite the extra code being generated in some cases. Patch is based on the original work of Tim Northover. Differential Revision: https://reviews.llvm.org/D46018 llvm-svn: 332449
* Emit a left-shift instead of a power-of-two multiply for jump-tablesAlexander Richardson2018-05-161-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: SelectionDAGLegalize::ExpandNode() inserts an ISD::MUL when lowering a BR_JT opcode. While many backends optimize this multiply into a shift, e.g. the MIPS backend currently always lowers this into a sequence of load-immediate+multiply+mflo in MipsSETargetLowering::lowerMulDiv(). I initially changed the multiply to a shift in the MIPS backend but it turns out that would not have handled the MIPSR6 case and was a lot more code than doing it in LegalizeDAG. I believe performing this simple optimization in LegalizeDAG instead of each individual backend is the better solution since this also fixes other backeds such as MSP430 which calls the multiply runtime function __mspabi_mpyi without this patch. Reviewers: sdardis, atanasyan, pftbest, asl Reviewed By: sdardis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45760 llvm-svn: 332439
* [DebugInfo] Only handle DBG_VALUE in InlineSpiller.Shiva Chen2018-05-161-2/+8
| | | | | | | | | | | | | The instructions using registers should be DBG_VALUE and normal instructions. Use isDebugValue() to filter out DBG_VALUE and add an assert to ensure there is no other kind of debug instructions using the registers. Differential Revision: https://reviews.llvm.org/D46739 Patch by Hsiangkai Wang. llvm-svn: 332427
* [MachineOutliner] Add optsize markings to outlined functions.Eli Friedman2018-05-151-0/+8
| | | | | | | | | It doesn't matter much this late in the pipeline, but one place that does check for it is the function alignment code. Differential Revision: https://reviews.llvm.org/D46373 llvm-svn: 332415
* Move helper classes into anonymous namespaces. NFCI.Benjamin Kramer2018-05-151-3/+3
| | | | llvm-svn: 332400
* [DAGCombine] Move load checks on store of loads into candidateNirav Dave2018-05-151-15/+13
| | | | | | | | | | search. NFCI. Migrate single-use and non-volatility, non-indexed requirements on stores of immediate store values to candidate collection pass from later stage. llvm-svn: 332392
* [DAG] propagate FMF for all FPMathOperatorsSanjay Patel2018-05-152-12/+29
| | | | | | | | | | | | | | | | | This is a simple hack based on what's proposed in D37686, but we can extend it if needed in follow-ups. It gets us most of the FMF functionality that we want without adding any state bits to the flags. It also intentionally leaves out non-FMF flags (nsw, etc) to minimize the patch. It should provide a superset of the functionality from D46563 - the extra tests show propagation and codegen diffs for fcmp, vecreduce, and FP libcalls. The PPC log2() test shows the limits of this most basic approach - we only applied 'afn' to the last node created for the call. AFAIK, there aren't any libcall optimizations based on the flags currently, so that shouldn't make any difference. Differential Revision: https://reviews.llvm.org/D46854 llvm-svn: 332358
* [CodeView] Improve debugging of virtual base class member variablesBrock Wyma2018-05-141-2/+1
| | | | | | | | Initial support for passing the virtual base pointer offset to CodeViewDebug. https://reviews.llvm.org/D46271 llvm-svn: 332296
* [BranchFolding] Allow hoisting to block with a single conditional branch.Geoff Berry2018-05-141-1/+5
| | | | | | | | | | | | | | | | | | | | | Summary: The BranchFolding pass is currently missing opportunities to hoist common code if the hoisted-to block contains a single conditional branch that has register uses. This occurs somewhat frequently on AArch64 with CBZ/TBZ opcodes. This change also eliminates some code differences when debug info is present since the presence of e.g. DBG_VALUE instructions in the hoisted-to block can enable hoisting that wouldn't have occurred without them. Reviewers: MatzeB, rnk, kparzysz, twoh, aprantl, javed.absar Subscribers: kristof.beyls, JDevlieghere, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46324 llvm-svn: 332265
* [CodeGen/AccelTable]: Handle -dwarf-linkage-names=Abstract correctlyPavel Labath2018-05-142-4/+7
| | | | | | | | | | | | | | | | | | | | Summary: If we are not emitting a linkage name in the .debug_info sections, we should not add it into the index either. This makes sure our index is consistent with the actual debug info. I am also explicitly setting the --dwarf-linkage-names=All in the name-collsions test as that one would now fail on targets where this defaults to "Abstract" (in fact, it would have failed already if there wasn't a bug in the DWARF verifier, which I fix as well). Reviewers: probinson, aprantl, JDevlieghere Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46748 llvm-svn: 332246
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-14110-2143/+2220
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* Fixing build bot error: adding const qualifiers to std::sort lambda.Puyan Lotfi2018-05-131-1/+1
| | | | | | Errors were not reproducible on clang-6.0 on ubuntu 16.04. llvm-svn: 332192
* [NFC] MIR-Canon: switching to a stable string sorting of instructions.Puyan Lotfi2018-05-131-2/+8
| | | | llvm-svn: 332191
* [DAG] add convenience function to propagate FMF; NFCSanjay Patel2018-05-111-7/+1
| | | | | | | | | There's only one use of this currently, but that could change with D46563. Either way, we shouldn't have to update code outside of the flags struct when those flag definitions change. llvm-svn: 332155
* [DAG] clean up flag propagation for binops; NFCISanjay Patel2018-05-112-36/+22
| | | | llvm-svn: 332150
* [DAG] reduce code duplication; NFCISanjay Patel2018-05-111-8/+7
| | | | llvm-svn: 332133
* [DAGCombiner] Set the right SDLoc on extended SETCC uses (7/N)Vedant Kumar2018-05-111-19/+13
| | | | | | | | | | | | | | | | | | | | ExtendSetCCUses updates SETCC nodes which use a load (OriginalLoad) to reflect a simplification to the load (ExtLoad). Based on my reading, ExtendSetCCUses may create new nodes to extend a constant attached to a SETCC. It also creates fresh SETCC nodes which refer to any updated operands. ISTM that the location applied to the new constant and SETCC nodes should be the same as the location of the ExtLoad. This was suggested by Adrian in https://reviews.llvm.org/D45995. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46216 llvm-svn: 332119
* [DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N)Vedant Kumar2018-05-111-38/+8
| | | | | | | | | | | | | | | | This teaches tryToFoldExtOfLoad to set the right location on a newly-created extload. With that in place, the logic for performing a certain ([s|z]ext (load ...)) combine becomes identical for sexts and zexts, and we can get rid of one copy of the logic. The test case churn is due to dependencies on IROrders inherited from the wrong SDLoc. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46158 llvm-svn: 332118
* [DAGCombiner] Factor out duplicated logic for an extload combine, NFC (5/N)Vedant Kumar2018-05-111-38/+52
| | | | | | | | | | | | | | | | Part of the logic for combining (zext (load ...)) and (sext (load ...)) is duplicated. This creates problems because bugs in one version have to be fixed again in the other version. To address this, as a first step, I've extracted the duplicate logic into a helper. I'll fix the debug location bug in the helper and eliminate the copy of its logic in a followup. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46157 llvm-svn: 332117
* Use iteration instead of recursion in CFIInserterSanjoy Das2018-05-111-15/+26
| | | | | | | | | | | | Summary: This recursive step can overflow the stack. Reviewers: djokov, petarj Subscribers: mcrosier, jlebar, bixia, llvm-commits Differential Revision: https://reviews.llvm.org/D46671 llvm-svn: 332101
* [STLExtras] Add distance() for ranges, pred_size(), and succ_size()Vedant Kumar2018-05-103-6/+3
| | | | | | | | | | | This commit adds a wrapper for std::distance() which works with ranges. As it would be a common case to write `distance(predecessors(BB))`, this also introduces `pred_size()` and `succ_size()` helpers to make that easier to write. Differential Revision: https://reviews.llvm.org/D46668 llvm-svn: 332057
* [DWARF] Fixing a bug in DWARF v5 string offsets tables where the length ↵Wolfgang Pieb2018-05-101-2/+2
| | | | | | | | | | | | | encoded the contribution length excluding the table header. Instead it must encode the contribution length minus the length field itself. Reviewer: JDevliegehere Differential Revision: https://reviews.llvm.org/D45922 llvm-svn: 332030
* [CGP] Split large data structres to sink more GEPsHaicheng Wu2018-05-101-26/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing the members of a large data structures needs a lot of GEPs which usually have large offsets due to the size of the underlying data structure. If the offsets are too large to fit into the r+i addressing mode, these GEPs cannot be sunk to their users' blocks and many extra registers are needed then to carry the values of these GEPs. This patch tries to split a large data struct starting from %base like the following. Before: BB0: %base = BB1: %gep0 = gep %base, off0 %gep1 = gep %base, off1 %gep2 = gep %base, off2 BB2: %load1 = load %gep0 %load2 = load %gep1 %load3 = load %gep2 After: BB0: %base = %new_base = gep %base, off0 BB1: %new_gep0 = %new_base %new_gep1 = gep %new_base, off1 - off0 %new_gep2 = gep %new_base, off2 - off0 BB2: %load1 = load i32, i32* %new_gep0 %load2 = load i32, i32* %new_gep1 %load3 = load i32, i32* %new_gep2 In the above example, the struct is split into two parts. The first part still starts from %base and the second part starts from %new_base. After the splitting, %new_gep1 and %new_gep2 have smaller offsets and then can be sunk to BB2 and folded into their users. The algorithm to split data structure is simple and very similar to the work of merging SExts. First, it collects GEPs that have large offsets when iterating the blocks. Second, it splits the underlying data structures and updates the collected GEPs to use smaller offsets. Differential Revision: https://reviews.llvm.org/D42759 llvm-svn: 332015
* [DAG] Avoid using deleted node in rebuildSetCCNirav Dave2018-05-101-8/+21
| | | | | | | | | | | | | | | | | Summary: The combine in rebuildSetCC may be combined to another node leaving our references stale. Keep a handle on it to avoid stale references. Fixes PR36602. Reviewers: dbabokin, RKSimon, eli.friedman, davide Subscribers: hiraditya, uabelho, JesperAntonsson, qcolombet, llvm-commits Differential Revision: https://reviews.llvm.org/D46404 llvm-svn: 331985
* [DWARF] Rework debug line parsing to use llvm::Error and callbacksJames Henderson2018-05-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewed by: dblaikie, JDevlieghere, espindola Differential Revision: https://reviews.llvm.org/D44560 Summary: The .debug_line parser previously reported errors by printing to stderr and return false. This is not particularly helpful for clients of the library code, as it prevents them from handling the errors in a manner based on the calling context. This change switches to using llvm::Error and callbacks to indicate what problems were detected during parsing, and has updated clients to handle the errors in a location-specific manner. In general, this means that they continue to do the same thing to external users. Below, I have outlined what the known behaviour changes are, relating to this change. There are two levels of "errors" in the new error mechanism, to broadly distinguish between different fail states of the parser, since not every failure will prevent parsing of the unit, or of subsequent unit. Malformed table errors that prevent reading the remainder of the table (reported by returning them) and other minor issues representing problems with parsing that do not prevent attempting to continue reading the table (reported by calling a specified callback funciton). The only example of this currently is when the last sequence of a unit is unterminated. However, I think it would be good to change the handling of unrecognised opcodes to report as minor issues as well, rather than just printing to the stream if --verbose is used (this would be a subsequent change however). I have substantially extended the DwarfGenerator to be able to handle custom-crafted .debug_line sections, allowing for comprehensive unit-testing of the parser code. For now, I am just adding unit tests to cover the basic error reporting, and positive cases, and do not currently intend to test every part of the parser, although the framework should be sufficient to do so at a later point. Known behaviour changes: - The dump function in DWARFContext now does not attempt to read subsequent tables when searching for a specific offset, if the unit length field of a table before the specified offset is a reserved value. - getOrParseLineTable now returns a useful Error if an invalid offset is encountered, rather than simply a nullptr. - The parse functions no longer use `WithColor::warning` directly to report errors, allowing LLD to call its own warning function. - The existing parse error messages have been updated to not specifically include "warning" in their message, allowing consumers to determine what severity the problem is. - If the line table version field appears to have a value less than 2, an informative error is returned, instead of just false. - If the line table unit length field uses a reserved value, an informative error is returned, instead of just false. - Dumping of .debug_line.dwo sections is now implemented the same as regular .debug_line sections. - Verbose dumping of .debug_line[.dwo] sections now prints the prologue, if there is a prologue error, just like non-verbose dumping. As a helper for the generator code, I have re-added emitInt64 to the AsmPrinter code. This previously existed, but was removed way back in r100296, presumably because it was dead at the time. This change also requires a change to LLD, which will be committed separately. llvm-svn: 331971
* [GlobalISel][Legalizer] Widening the second src op of shifts bug fixRoman Tereshin2018-05-091-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | The second source operand of G_SHL, G_ASHR, and G_LSHR must preserve its value as a (small) unsigned integer, therefore its incorrect to widen it in any way but by zero extending it. G_SHL was using G_ANYEXT and G_ASHR - G_SEXT (which is correct for their destination and first source operands, but not the "number of bits to shift" operand). Generally, shifts aren't as similar to regular binary operations as it might seem, for instance, they aren't commutative nor associative and the second source operand usually requires a special treatment. Reviewers: bogner, javed.absar, aivchenk, rovka Reviewed By: bogner Subscribers: igorb, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46413 llvm-svn: 331926
* Reapplying r331819 [GlobalISel][Legalizer] More concise and faster ↵Roman Tereshin2018-05-092-236/+144
| | | | | | | | | widenScalar, NFC The commit was a suspect for clang-cmake-aarch64-global-isel and clang-cmake-aarch64-quick bot failures, proved to be innocent. llvm-svn: 331898
* [DAGCombiner] In visitBITCAST when trying to constant fold the bitcast, only ↵Craig Topper2018-05-091-11/+11
| | | | | | | | | | call getBitcast if its an fp->int or int->fp conversion even when before legalize ops. Previously if !LegalOperations we would blindly call getBitcast and hope that getNode would constant fold it. But if the conversion is between a vector and a scalar, getNode has no simplification. This means we would just get back the original N. We would then return that N which would make the caller of visitBITCAST think that we used CombineTo and did our own worklist management. This prevents target specific optimizations from being called for vector/scalar bitcasts until after legal operations. llvm-svn: 331896
* [DAGCombine] Change store merge candidates check cut off to 1024.Amara Emerson2018-05-091-1/+1
| | | | | | | | | | | The previous value of 8192 resulted in severe compile time hits in some pathological cases. rdar://39781410 Differential Revision: https://reviews.llvm.org/D46581 llvm-svn: 331888
* Revert r331816 and r331820 - [globalisel] Add a combiner helpers for ↵Daniel Sanders2018-05-091-33/+1
| | | | | | | | | | extending loads and use them in a pre-legalize combiner for AArch64 Reverting this to see if the clang-cmake-aarch64-global-isel and clang-cmake-aarch64-quick bots are failing because of this commit. We know it wasn't r331819. llvm-svn: 331846
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-0936-87/+98
| | | | | | | | | | | | | | | | | | Because we create a new kind of debug instruction, DBG_LABEL, we need to check all passes which use isDebugValue() to check MachineInstr is debug instruction or not. When expelling debug instructions, we should expel both DBG_VALUE and DBG_LABEL. So, I create a new function, isDebugInstr(), in MachineInstr to check whether the MachineInstr is debug instruction or not. This patch has no new test case. I have run regression test and there is no difference in regression test. Differential Revision: https://reviews.llvm.org/D45342 Patch by Hsiangkai Wang. llvm-svn: 331844
* [DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr.Shiva Chen2018-05-099-0/+141
| | | | | | | | | | | | | | | | | | | | | In order to convert LLVM IR to MachineInstr, we need a new TargetOpcode, DBG_LABEL, to ‘lower’ intrinsic llvm.dbg.label. The patch creates this new TargetOpcode and convert intrinsic llvm.dbg.label to MachineInstr through SelectionDAG. In SelectionDAG, debug information is stored in SDDbgInfo. We create a new data member of SDDbgInfo for labels and use the new data member, SDDbgLabel, to create DBG_LABEL MachineInstr. The new DBG_LABEL MachineInstr uses label metadata from LLVM IR as its parameter. So, the backend could get metadata information of labels from DBG_LABEL MachineInstr. Differential Revision: https://reviews.llvm.org/D45341 Patch by Hsiangkai Wang. llvm-svn: 331842
* [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen2018-05-092-12/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to set breakpoints on labels and list source code around labels, we need collect debug information for labels, i.e., label name, the function label belong, line number in the file, and the address label located. In order to keep these information in LLVM IR and to allow backend to generate debug information correctly. We create a new kind of metadata for labels, DILabel. The format of DILabel is !DILabel(scope: !1, name: "foo", file: !2, line: 3) We hope to keep debug information as much as possible even the code is optimized. So, we create a new kind of intrinsic for label metadata to avoid the metadata is eliminated with basic block. The intrinsic will keep existing if we keep it from optimized out. The format of the intrinsic is llvm.dbg.label(metadata !1) It has only one argument, that is the DILabel metadata. The intrinsic will follow the label immediately. Backend could get the label metadata through the intrinsic's parameter. We also create DIBuilder API for labels to be used by Frontend. Frontend could use createLabel() to allocate DILabel objects, and use insertLabel() to insert llvm.dbg.label intrinsic in LLVM IR. Differential Revision: https://reviews.llvm.org/D45024 Patch by Hsiangkai Wang. llvm-svn: 331841
* Revert r331819 [GlobalISel][Legalizer] More concise and faster widenScalar, NFCRoman Tereshin2018-05-092-144/+236
| | | | | | | Reverting this to see if the clang-cmake-aarch64-global-isel and clang-cmake-aarch64-quick bots are failing because of this commit llvm-svn: 331839
* [globalisel] Correct r331816 to check the opcode before calling getOperand().Daniel Sanders2018-05-081-4/+4
| | | | | | | | | Fix a silly mistake in my pre-commit changes for r331816. It should check what opcode the insn is before extracting the operands. NFC at the moment since the caller already checked the opcode. llvm-svn: 331820
* [GlobalISel][Legalizer] More concise and faster widenScalar, NFCRoman Tereshin2018-05-082-236/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactoring LegalizerHelper::widenScalar member function reducing its size by approximately a factor of 2 and (hopefuly) making it more straightforward and regular by introducing widenScalarSrc and widenScalarDst helper methods. The new widenScalar* methods mutate the instructions in place instead of recreating them from scratch and removing the originals. The compile time implications of this were measured on sqlite3 amalgamation, targeting AArch64 in -O0: LegalizerHelper::widenScalar: > 25% faster Legalizer::runOnMachineFunction: ~ 4.0 - 4.5% faster Also adding MachineOperand::setCImm and refactoring out MachineIRBuilder::recordInsertion methods to make the change possible. Reviewers: aditya_nandakumar, bogner, javed.absar, t.p.northover, ab, dsanders, arsenm Reviewed By: aditya_nandakumar Subscribers: wdng, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46414 llvm-svn: 331819
* [globalisel] Add a combiner helpers for extending loads and use them in a ↵Daniel Sanders2018-05-081-1/+33
| | | | | | | | | | | | | | | | pre-legalize combiner for AArch64 Summary: Depends on D45541 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson Reviewed By: aemerson Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45543 llvm-svn: 331816
* [AsmPrinter] Allow emitting codeview for any windows targetMartin Storsjo2018-05-081-2/+1
| | | | | | | | | | | | | | | | Before SVN r244158, codeview debug info was emitted always emitted for msvc if debug info was enabled, but that commit added a module flag. Since it's still restricted by the flag, we can allow it for any target if the user requests it, not only msvc (and windows-itanium, added in SVN r287567). Add a test for emitting it for a mingw target. Differential Revision: https://reviews.llvm.org/D46303 llvm-svn: 331809
* DAG: Use correct shift width typeMatt Arsenault2018-05-081-1/+1
| | | | llvm-svn: 331792
* [CodeGenPrepare] Move Extension Instructions Through Logical And Shift ↵Guozhi Wei2018-05-081-0/+41
| | | | | | | | | | Instructions CodeGenPrepare pass move extension instructions close to load instructions in different BB, so they can be combined later. But the extension instructions can't move through logical and shift instructions in current implementation. This patch enables this enhancement, so we can eliminate more extension instructions. Differential Revision: https://reviews.llvm.org/D45537 llvm-svn: 331783
* [MachineVerifier][GlobalISel] Verifying generic extends and truncatesRoman Tereshin2018-05-081-0/+52
| | | | | | | | | | | | | | | | | Making sure we don't truncate / extend pointers, don't try to change vector topology or bitcast vectors to scalars or back, and most importantly, don't extend to a smaller type or truncate to a large one. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331718
* [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)Roman Tereshin2018-05-081-13/+20
| | | | | | | | | | | | | | MIParser wasn't able to parse LLTs like `<4 x p0>`, fixing that. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331712
* [MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all ↵Roman Tereshin2018-05-072-6/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | vregs Every generic machine instruction must have generic virtual registers only, that is, have a low-level type attached to each operand. Previously MachineVerifier would catch a type missing on an operand only if the previous operand for the the same type index exists and have a type attached to it and it will report it as a type mismatch. This is incosistent behaviour and a misleading error message. This commit makes sure MachineVerifier explicitly checks that the types are there for every operand and if not provides a straightforward error message. Reviewers: qcolombet t.p.northover bogner ab Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46455 llvm-svn: 331694
* [MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring ↵Roman Tereshin2018-05-072-21/+28
| | | | | | | | | | | | | | | | | | | | visitMachineInstrBefore This is an NFC pre-commit for the following "Checking that generic instrs have LLTs on all vregs" commit. This overloads MachineOperand::print to make it possible to print LLTs with standalone machine operands. This also overloads MachineVerifier::print(...MachineOperand...) with an optional LLT using the newly introduced MachineOperand::print variant; no actual calls added. This also refactors MachineVerifier::visitMachineInstrBefore in the parts dealing with all generic instructions (checking Selected property, LLTs, and phys regs). llvm-svn: 331693
* [DAGCombiner] Masked merge: enhance handling of 'andn' with immediatesRoman Lebedev2018-05-071-4/+14
| | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. The previous patch, D46493, completely disabled unfolding in case of immediates. But we can do better: {F6120274} {F6120277} https://rise4fun.com/Alive/xJS Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D46494 llvm-svn: 331685
* [DagCombiner] Not all 'andn''s work with immediates.Roman Lebedev2018-05-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. In masked merge case, this degrades IPC by decreasing instruction count. {F6108777} The next patch should be able to recover and improve this. This also affects the transform @spatel have added in D27489 / rL289738, and the test coverage for X86 was missing. But after i have added it, and looked at the changes in MCA, i'm somewhat confused. {F6093591} {F6093592} {F6093593} I'd say this regression is an improvement, since `IPC` increased in that case? Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D46493 llvm-svn: 331684
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