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* Fix a nasty bug from a previous patch of mineChris Lattner2005-08-261-1/+1
| | | | llvm-svn: 23069
* New fold for SELECT_CCNate Begeman2005-08-251-1/+19
| | | | llvm-svn: 23058
* Don't auto-cse nodes that return flagsChris Lattner2005-08-251-17/+38
| | | | llvm-svn: 23055
* add printer support for flag operandsChris Lattner2005-08-251-0/+1
| | | | llvm-svn: 23054
* simplify the code a bit using isOperationLegalChris Lattner2005-08-251-4/+3
| | | | llvm-svn: 23053
* Add support for flag operandsChris Lattner2005-08-251-8/+18
| | | | llvm-svn: 23050
* ADd support for TargetConstantPool nodesChris Lattner2005-08-251-1/+14
| | | | llvm-svn: 23041
* add a new TargetFrameIndex nodeChris Lattner2005-08-251-1/+13
| | | | llvm-svn: 23035
* add a methodChris Lattner2005-08-241-0/+6
| | | | llvm-svn: 23027
* Add ReplaceAllUsesWith that can take a vector of replacement values.Chris Lattner2005-08-241-15/+90
| | | | | | Add some foldings to hopefully help the illegal setcc issue, and move some code around. llvm-svn: 23025
* Add support for external symbols, and support for variable arity instructionsChris Lattner2005-08-241-5/+12
| | | | llvm-svn: 23022
* Fix pasto that prevented VT ndoes from showing up in -view-isel-dags correctlyChris Lattner2005-08-241-1/+1
| | | | llvm-svn: 23021
* teach selection dag mask tracking about the fact that select_cc operates likeChris Lattner2005-08-241-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | select. Also teach it that the bit count instructions can only set the low bits of the result, depending on the size of the input. This allows us to compile this: int %eq0(int %a) { %tmp.1 = seteq int %a, 0 ; <bool> [#uses=1] %tmp.2 = cast bool %tmp.1 to int ; <int> [#uses=1] ret int %tmp.2 } To this: _eq0: cntlzw r2, r3 srwi r3, r2, 5 blr instead of this: _eq0: cntlzw r2, r3 rlwinm r3, r2, 27, 31, 31 blr when setcc is marked illegal on ppc (which restores parity to non-illegal setcc). Thanks to Nate for pointing this out. llvm-svn: 23013
* Start using isOperationLegal and isTypeLegal to simplify the codeChris Lattner2005-08-241-28/+23
| | | | llvm-svn: 23012
* Teach SelectionDAG how to simplify a few more setcc-equivalent select_ccNate Begeman2005-08-241-6/+21
| | | | | | nodes so that backends don't have to. llvm-svn: 22999
* Make -view-isel-dags show the dag before instruction selecting, in caseChris Lattner2005-08-241-2/+2
| | | | | | the target isel crashes due to unimplemented features like calls :) llvm-svn: 22997
* Fix optimization of select_cc seteq X, 0, 1, 0 -> srl (ctlz X), log2 X sizeNate Begeman2005-08-241-3/+3
| | | | llvm-svn: 22995
* Implement LiveVariables.h changeChris Lattner2005-08-241-0/+30
| | | | llvm-svn: 22994
* adjust to new live variables interfaceChris Lattner2005-08-233-35/+32
| | | | llvm-svn: 22992
* Simplify this code by using higher-level LiveVariables methodsChris Lattner2005-08-231-20/+10
| | | | llvm-svn: 22989
* Keep track of which registers are related to which other registers.Chris Lattner2005-08-231-21/+86
| | | | | | | | | | | | | Use this information to avoid doing expensive interval intersections for registers that could not possible be interesting. This speeds up linscan on ia64 compiling kc++ in release mode from taking 7.82s to 4.8s(!), total itanium llc time on this program is 27.3s now. This marginally speeds up PPC and X86, but they appear to be limited by other parts of linscan, not this code. On this program, on itanium, live intervals now takes 41% of llc time. llvm-svn: 22986
* Teach the SelectionDAG how to transform select_cc eq, X, 0, 1, 0 intoNate Begeman2005-08-231-0/+17
| | | | | | | either seteq X, 0 or srl (ctlz X), size(X-1), depending on what's legal for the target. llvm-svn: 22978
* Teach Legalize how to turn setcc into select_ccNate Begeman2005-08-231-18/+31
| | | | llvm-svn: 22977
* Try to avoid scanning the fixed list. On architectures with a non-stupidChris Lattner2005-08-221-20/+55
| | | | | | | | | | | | | number of regs (e.g. most riscs), many functions won't need to use callee clobbered registers. Do a speculative check to see if we can get a free register without processing the fixed list (which has all of these). This saves a lot of time on machines with lots of callee clobbered regs (e.g. ppc and itanium, also x86). This reduces ppc llc compile time from 184s -> 172s on kc++. This is probably worth FAR FAR more on itanium though. llvm-svn: 22972
* Move some code in the register assignment case that only needs to happen ifChris Lattner2005-08-221-17/+26
| | | | | | | | we spill out of the fast path. The scan of active_ and the calls to updateSpillWeights don't need to happen unless a spill occurs. This reduces debug llc time of kc++ with ppc from 187.3s to 183.2s. llvm-svn: 22971
* Fix a problem where constant expr shifts would not have their shift amountChris Lattner2005-08-221-5/+5
| | | | | | promoted to the right type. This fixes: IA64/2005-08-22-LegalizerCrash.ll llvm-svn: 22969
* Speed up this loop a bit, based on some observations that Nate made, andChris Lattner2005-08-221-8/+34
| | | | | | add some comments. This loop really needs to be reevaluated! llvm-svn: 22966
* Add a fast-path for register values. Add support for constant pool entries,Chris Lattner2005-08-221-1/+13
| | | | | | | | | | | | | | | | | | | | | allowing us to compile this: float %test2(float* %P) { %Q = load float* %P %R = add float %Q, 10.1 ret float %R } to this: _test2: lfs r2, 0(r3) lis r3, ha16(.CPI_test2_0) lfs r3, lo16(.CPI_test2_0)(r3) fadds f1, r2, r3 blr llvm-svn: 22962
* add anew methodChris Lattner2005-08-211-0/+10
| | | | llvm-svn: 22957
* Add support for frame index nodesChris Lattner2005-08-211-3/+4
| | | | llvm-svn: 22956
* add a methodChris Lattner2005-08-211-0/+9
| | | | llvm-svn: 22955
* add a methodChris Lattner2005-08-211-0/+9
| | | | llvm-svn: 22949
* Add support for basic blocks, fix a bug in result # computationChris Lattner2005-08-211-2/+7
| | | | llvm-svn: 22948
* When legalizing brcond ->brcc or select -> selectcc, make sure to truncateChris Lattner2005-08-211-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the old condition to a one bit value. The incoming value must have been promoted, and the top bits are undefined. This causes us to generate: _test: rlwinm r2, r3, 0, 31, 31 li r3, 17 cmpwi cr0, r2, 0 bne .LBB_test_2 ; .LBB_test_1: ; li r3, 1 .LBB_test_2: ; blr instead of: _test: rlwinm r2, r3, 0, 31, 31 li r2, 17 cmpwi cr0, r3, 0 bne .LBB_test_2 ; .LBB_test_1: ; li r2, 1 .LBB_test_2: ; or r3, r2, r2 blr for: int %test(bool %c) { %retval = select bool %c, int 17, int 1 ret int %retval } llvm-svn: 22947
* fix bogus warningChris Lattner2005-08-201-1/+1
| | | | llvm-svn: 22943
* Add support for global address nodesChris Lattner2005-08-191-0/+3
| | | | llvm-svn: 22940
* Add support for TargetGlobalAddress nodesChris Lattner2005-08-191-1/+14
| | | | llvm-svn: 22938
* Implement CopyFromReg, TokenFactor, and fix a bug in CopyToReg. This allowsChris Lattner2005-08-191-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | us to compile stuff like this: double %test(double %A, double %B, double %C, double %E) { %F = mul double %A, %A %G = add double %F, %B %H = sub double -0.0, %G %I = mul double %H, %C %J = add double %I, %E ret double %J } to: _test: fnmadd f0, f1, f1, f2 fmadd f1, f0, f3, f4 blr woot! llvm-svn: 22937
* Fix a bug in previous commitChris Lattner2005-08-191-1/+2
| | | | llvm-svn: 22936
* Print physreg register nodes with target names (e.g. F1) instead of numbersChris Lattner2005-08-192-2/+12
| | | | llvm-svn: 22934
* Before implementing copyfromreg, we'll implement copytoreg correctly.Chris Lattner2005-08-191-2/+6
| | | | | | | | | | | | | This gets us this for the previous testcase: _test: lis r2, 0 ori r3, r2, 65535 blr Note that we actually write to r3 (the return reg) correctly now :) llvm-svn: 22933
* Now that we have operand info for machine instructions, use it to createChris Lattner2005-08-191-8/+21
| | | | | | | | | | | | | | | | | | temporary registers for things that define a register. This allows dag->dag isel to compile this: int %test() { ret int 65535 } into: _test: lis r2, 0 ori r2, r2, 65535 blr Next up, getting CopyFromReg to work, allowing arguments and cross-bb values. llvm-svn: 22932
* Fix VC++ constant truncation warning.Jeff Cohen2005-08-191-2/+2
| | | | llvm-svn: 22907
* Fix VC++ precedence warning.Jeff Cohen2005-08-191-1/+1
| | | | llvm-svn: 22902
* Fix computation of # operands, add a temporary hack for CopyToRegChris Lattner2005-08-191-6/+17
| | | | llvm-svn: 22896
* add a new -view-sched-dags option to view dags as they are sent to the ↵Chris Lattner2005-08-181-0/+10
| | | | | | scheduler. llvm-svn: 22878
* Implement the first chunk of a code emitter. This is sophisticated enough toChris Lattner2005-08-181-1/+94
| | | | | | | | | | | | codegen: _empty: .LBB_empty_0: ; blr but can't do anything more (yet). :) llvm-svn: 22876
* new file, obviously just a stubChris Lattner2005-08-181-0/+23
| | | | llvm-svn: 22868
* Enable critical edge splitting by defaultChris Lattner2005-08-181-16/+10
| | | | llvm-svn: 22863
* Add support for target DAG nodes that take 4 operands, such as PowerPC'sNate Begeman2005-08-181-0/+8
| | | | | | rlwinm. llvm-svn: 22856
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