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authorChris Lattner <sabre@nondot.org>2005-08-19 21:43:53 +0000
committerChris Lattner <sabre@nondot.org>2005-08-19 21:43:53 +0000
commit6d7f814b014791d9fc0b645bf2572accc44a9a92 (patch)
tree4dff94deb94ab7acddb53d043a95d38dbe4fa7c2 /llvm/lib/CodeGen
parent0875d1ab896690d4671bbcc0465e734e601946d2 (diff)
downloadbcm5719-llvm-6d7f814b014791d9fc0b645bf2572accc44a9a92.tar.gz
bcm5719-llvm-6d7f814b014791d9fc0b645bf2572accc44a9a92.zip
Implement CopyFromReg, TokenFactor, and fix a bug in CopyToReg. This allows
us to compile stuff like this: double %test(double %A, double %B, double %C, double %E) { %F = mul double %A, %A %G = add double %F, %B %H = sub double -0.0, %G %I = mul double %H, %C %J = add double %I, %E ret double %J } to: _test: fnmadd f0, f1, f1, f2 fmadd f1, f0, f3, f4 blr woot! llvm-svn: 22937
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp30
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index d77578e2866..e7827a8acf6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -131,13 +131,43 @@ unsigned SimpleSched::Emit(SDOperand Op) {
Op.Val->dump();
assert(0 && "This target-independent node should have been selected!");
case ISD::EntryToken: break;
+ case ISD::TokenFactor:
+ for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
+ Emit(Op.getOperand(i));
+ break;
case ISD::CopyToReg: {
+ Emit(Op.getOperand(0)); // Emit the chain.
unsigned Val = Emit(Op.getOperand(2));
MRI.copyRegToReg(*BB, BB->end(),
cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
RegMap->getRegClass(Val));
break;
}
+ case ISD::CopyFromReg: {
+ Emit(Op.getOperand(0)); // Emit the chain.
+ unsigned SrcReg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
+
+ // Figure out the register class to create for the destreg.
+ const TargetRegisterClass *TRC;
+ if (MRegisterInfo::isVirtualRegister(SrcReg)) {
+ TRC = RegMap->getRegClass(SrcReg);
+ } else {
+ // FIXME: we don't know what register class to generate this for. Do
+ // a brute force search and pick the first match. :(
+ for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
+ E = MRI.regclass_end(); I != E; ++I)
+ if ((*I)->contains(SrcReg)) {
+ TRC = *I;
+ break;
+ }
+ assert(TRC && "Couldn't find register class for reg copy!");
+ }
+
+ // Create the reg, emit the copy.
+ ResultReg = RegMap->createVirtualRegister(TRC);
+ MRI.copyRegToReg(*BB, BB->end(), ResultReg, SrcReg, TRC);
+ break;
+ }
}
}
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