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* [FaultMaps] Add a parser for the __llvm__faultmaps section.Sanjoy Das2015-06-221-0/+37
| | | | | | | | | | | | | | | Summary: The parser is exercised by llvm-objdump using -print-fault-maps. As is probably obvious, the code itself was "heavily inspired" by http://reviews.llvm.org/D10434. Reviewers: reames, atrick, JosephTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10491 llvm-svn: 240304
* Avoid a Symbol -> Name -> Symbol conversion.Rafael Espindola2015-06-226-6/+24
| | | | | | | | | | | | | | Before this we were producing a TargetExternalSymbol from a MCSymbol. That meant extracting the symbol name and fetching the symbol again down the pipeline. This patch adds a DAG.getMCSymbol that lets the MCSymbol pass unchanged on the DAG. Doing so removes the need for MO_NOPREFIX and fixes the root cause of pr23900, allowing r240130 to be committed again. llvm-svn: 240300
* MIR Serialization: Serialize machine instruction names.Alex Lorenz2015-06-225-3/+185
| | | | | | | | | | | | | | | | This commit implements initial machine instruction serialization. It serializes machine instruction names. The instructions are represented using a YAML sequence of string literals and are a part of machine basic block YAML mapping. This commit introduces a class called 'MIParser' which will be used to parse the machine instructions and operands. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10481 llvm-svn: 240295
* Fix shl folding in DAG combiner.Pawel Bylica2015-06-221-1/+1
| | | | | | | | | | | | | | | | Summary: The code responsible for shl folding in the DAGCombiner was assuming incorrectly that all constants are less than 64 bits. This patch simply changes the way values are compared. Test Plan: A regression test included. Reviewers: andreadb Reviewed By: andreadb Subscribers: andreadb, test, llvm-commits Differential Revision: http://reviews.llvm.org/D10602 llvm-svn: 240291
* [PM/AA] Hoist the AliasResult enum out of the AliasAnalysis class.Chandler Carruth2015-06-222-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This will allow classes to implement the AA interface without deriving from the class or referencing an internal enum of some other class as their return types. Also, to a pretty fundamental extent, concepts such as 'NoAlias', 'MayAlias', and 'MustAlias' are first class concepts in LLVM and we aren't saving anything by scoping them heavily. My mild preference would have been to use a scoped enum, but that feature is essentially completely broken AFAICT. I'm extremely disappointed. For example, we cannot through any reasonable[1] means construct an enum class (or analog) which has scoped names but converts to a boolean in order to test for the possibility of aliasing. [1]: Richard Smith came up with a "solution", but it requires class templates, and lots of boilerplate setting up the enumeration multiple times. Something like Boost.PP could potentially bundle this up, but even that would be quite painful and it doesn't seem realistically worth it. The enum class solution would probably work without the need for a bool conversion. Differential Revision: http://reviews.llvm.org/D10495 llvm-svn: 240255
* AsmPrinter: Don't emit empty .debug_loc entriesDuncan P. N. Exon Smith2015-06-215-14/+122
| | | | | | | | | | | If we don't know how to represent a .debug_loc entry, skip the entry entirely rather than emitting an empty one. Similarly, if a .debug_loc list has no entries, don't create the list. We still want to create the variables, just in an optimized-out form that doesn't have a DW_AT_location. llvm-svn: 240244
* AsmPrinter: Rewrite initialization of DbgVariable, NFCDuncan P. N. Exon Smith2015-06-213-64/+85
| | | | | | | | | | | | | | | | | | | | | | | There are three types of `DbgVariable`: - alloca variables, created based on the MMI table, - register variables, created based on DBG_VALUE instructions, and - optimized-out variables. This commit reconfigures `DbgVariable` to make it easier to tell which kind we have, and make initialization a little clearer. For MMI/alloca variables, `FrameIndex.size()` must always equal `Expr.size()`, and there shouldn't be an `MInsn`. For register variables (with a `MInsn`), `FrameIndex` must be empty, and `Expr` should have 0 or 1 element depending on whether it has a complex expression (registers with multiple locations use `DebugLocListIndex`). Optimized-out variables shouldn't have any of these fields. Moreover, this separates DBG_VALUE initialization until after the variable is created, simplifying logic in a future commit that changes `collectVariableInfo()` to stop creating empty .debug_loc entries/lists. llvm-svn: 240243
* Switch lowering: add heuristic for filling leaf nodes in the weight-balanced ↵Hans Wennborg2015-06-202-0/+59
| | | | | | | | | | | | | | | | | | binary search tree Sparse switches with profile info are lowered as weight-balanced BSTs. For example, if the node weights are {1,1,1,1,1,1000}, the right-most node would end up in a tree by itself, bringing it closer to the top. However, a leaf in this BST can contain up to 3 cases, and having a single case in a leaf node as in the example means the tree might become unnecessarily high. This patch adds a heauristic to the pivot selection algorithm that moves more cases into leaf nodes unless that would lower their rank. It still doesn't yield the optimal tree in every case, but I believe it's conservatibely correct. llvm-svn: 240224
* Reformat.NAKAMURA Takumi2015-06-201-7/+12
| | | | llvm-svn: 240213
* Revert r240040, "[BranchFolding] Replace custom MachineInstr with ↵NAKAMURA Takumi2015-06-201-6/+46
| | | | | | | | MachineInstrExpressionTrait" It caused different emission between stage2 and stage3. Investigating. llvm-svn: 240212
* [Statepoint] Remove unnecessary argument from Statepoint::getRelocatesSanjoy Das2015-06-201-4/+2
| | | | | | NFC. llvm-svn: 240198
* name change: hasPattern() -> getMachineCombinerPatterns() ; NFCSanjay Patel2015-06-191-5/+5
| | | | | | | This was suggested as part of D10460, but it's independent of any functional change. llvm-svn: 240192
* MIR Parser: report an error when a basic block isn't found.Alex Lorenz2015-06-191-1/+3
| | | | | | | This commit reports an error when the MIR parser can't find a basic block with the machine basic block's name. llvm-svn: 240174
* MIR Serialization: Serialize the list of machine basic blocks with simple ↵Alex Lorenz2015-06-192-0/+50
| | | | | | | | | | | | | | attributes. This commit implements the initial serialization of machine basic blocks in a machine function. Only the simple, scalar MBB attributes are serialized. The reference to LLVM IR's basic block is preserved when that basic block has a name. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10465 llvm-svn: 240145
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-1970-87/+87
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* Fix "the the" in comments.Eric Christopher2015-06-194-5/+5
| | | | llvm-svn: 240112
* Avoid redundant select node in early if-conversion passYi Jiang2015-06-181-4/+13
| | | | llvm-svn: 240072
* Switch lowering: enable whole-switch jump tables at -O0.Hans Wennborg2015-06-181-15/+31
| | | | | | | | To same compile time, the analysis to find dense case-clusters in switches is not done at -O0. However, when the whole switch is dense enough, it is easy to turn it into a jump table, resulting in much faster code with no extra effort. llvm-svn: 240071
* [BranchFolding] Replace custom MachineInstr with MachineInstrExpressionTraitBenjamin Kramer2015-06-181-46/+6
| | | | | | | While the hash functions are subtly different it shouldn't have an impact. Instructions are checked with isIdenticalTo later. llvm-svn: 240040
* [CodeGen] Don't emit a random reference to the personality functionDavid Majnemer2015-06-181-4/+0
| | | | | | This should fix issues we've been seeing with Darwin. llvm-svn: 240036
* fix typo; NFCSanjay Patel2015-06-181-4/+4
| | | | llvm-svn: 240022
* [AsmPrinter] Make isRepeatedByteSequence smarter about odd integer typesBenjamin Kramer2015-06-171-26/+16
| | | | | | | | | | | | - zext the value to alloc size first, then check if the value repeats with zero padding included. If so we can still emit a .space - Do the checking with APInt.isSplat(8), which handles non-pow2 types - Also handle large constants (bit width > 64) - In a ConstantArray all elements have the same type, so it's sufficient to check the first constant recursively and then just compare if all following constants are the same by pointer compare llvm-svn: 239977
* remove unnecessary casts; NFCSanjay Patel2015-06-171-4/+2
| | | | llvm-svn: 239942
* Move the personality function from LandingPadInst to FunctionDavid Majnemer2015-06-177-30/+36
| | | | | | | | | | | | | | | | | | | The personality routine currently lives in the LandingPadInst. This isn't desirable because: - All LandingPadInsts in the same function must have the same personality routine. This means that each LandingPadInst beyond the first has an operand which produces no additional information. - There is ongoing work to introduce EH IR constructs other than LandingPadInst. Moving the personality routine off of any one particular Instruction and onto the parent function seems a lot better than have N different places a personality function can sneak onto an exceptional function. Differential Revision: http://reviews.llvm.org/D10429 llvm-svn: 239940
* [CodeGenPrepare] Generalize inserted set from truncs to any inst.Ahmed Bougacha2015-06-171-21/+28
| | | | | | | | | It's been used before to avoid infinite loops caused by separate CGP optimizations undoing one another. We found one more such issue caused by r238054. To avoid it, generalize the "InsertedTruncs" set to any inst, and use it to avoid touching those again. llvm-svn: 239938
* fix typos in comments; NFCSanjay Patel2015-06-171-2/+2
| | | | llvm-svn: 239916
* [PM/AA] Remove the Location typedef from the AliasAnalysis class nowChandler Carruth2015-06-174-23/+18
| | | | | | | | | | | | that it is its own entity in the form of MemoryLocation, and update all the callers. This is an entirely mechanical change. References to "Location" within AA subclases become "MemoryLocation", and elsewhere "AliasAnalysis::Location" becomes "MemoryLocation". Hope that helps out-of-tree folks update. llvm-svn: 239885
* Rename and improve emitSectionOffset.Rafael Espindola2015-06-164-29/+19
| | | | | | | | | | | | | | | | | | | | | | | Different object formats represent references from dwarf in different ways. ELF uses a relocation to the referenced point (except for .dwo) and COFF/MachO use the offset of the referenced point inside its section. This patch renames emitSectionOffset because * It doesn't produce an offset on ELF. * It changes behavior depending on how DWARF is represented, so adding dwarf to its name is probably a good thing. The patch also adds an option to force the use of offsets.That avoids funny looking code like if (!UseOffsets) Asm->emitSectionOffset.... It was correct, but read as if the ! was inverted. llvm-svn: 239866
* rename variables; NFCSanjay Patel2015-06-161-13/+13
| | | | | | ...because I see 'StoreBW' and read it as 'store bandwidth' llvm-svn: 239850
* extract some code into a helper function for MergeConsecutiveStores(); NFCISanjay Patel2015-06-161-43/+57
| | | | llvm-svn: 239847
* VirtRegMap: Add undef flag when reading undefined subregisters.Matthias Braun2015-06-161-18/+63
| | | | | | | | | | | | | | | | | While completely undefined registers are easy to catch and get their <undef> flag early in ProcessImplicitDefs/RegisterCoalescer reading from a partially defined register where just the subreg happens to be undefined is harder to catch so we only add the undef flag in the virtual register rewriting step. No testcase as I cannot reproduce the problem on any of the in-tree targets at the moment. This fixes rdar://21387089 Differential Revision: http://reviews.llvm.org/D10470 llvm-svn: 239838
* TargetRegisterInfo: Make the concept of imprecise lane masks explicitMatthias Braun2015-06-161-1/+2
| | | | | | | | | | | | | | | | | | | | LaneMasks as given by getSubRegIndexLaneMask() have a limited number of of bits, so for targets with more than 31 disjunct subregister there may be cases where: getSubReg(Reg,A) does not overlap getSubReg(Reg,B) but we still have (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0. I had hoped to keep this an implementation detail of the tablegen but as my next commit shows we can avoid unnecessary imp-defs operands if we know that the lane masks in use are precise. This is in preparation to http://reviews.llvm.org/D10470. llvm-svn: 239837
* MIR Parser: Report an error when a machine function doesn't have a ↵Alex Lorenz2015-06-161-0/+3
| | | | | | | | | | | | | corresponding function. This commit reports an error when a machine function from a MIR file that contains LLVM IR can't find a function with the same name in the loaded LLVM IR module. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10468 llvm-svn: 239831
* propagate IR-level fast-math-flags to DAG nodes, disabled by defaultSanjay Patel2015-06-164-51/+63
| | | | | | | | | | | | | | | | | | | | | | | This is an updated version of the patch that was checked in at: http://reviews.llvm.org/rL237046 but subsequently reverted because it exposed a bug in the DAG Combiner: http://reviews.llvm.org/D9893 This time, there's an enablement flag ("EnableFMFInDAG") around the code in SelectionDAGBuilder where we copy the set of FP optimization flags from IR instructions to DAG nodes. So, in theory, there should be no functional change from this patch as-is, but it will allow testing with the added functionality to proceed via "-enable-fmf-dag" passed to llc. This patch adds the minimum plumbing necessary to use IR-level fast-math-flags (FMF) in the backend without actually using them for anything yet. This is a follow-on to: http://reviews.llvm.org/rL235997 Differential Revision: http://reviews.llvm.org/D10403 llvm-svn: 239828
* Revert "Revert "Fix merges of non-zero vector stores""Matt Arsenault2015-06-161-6/+20
| | | | | | | | Reapply r239539. Don't assume the collected number of stores is the same vector size. Just take the first N stores to fill the vector. llvm-svn: 239825
* Replace string GNU Triples with llvm::Triple in ↵Daniel Sanders2015-06-162-17/+18
| | | | | | | | | | | | | | | | | | TargetMachine::getTargetTriple(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rengolin Reviewed By: rengolin Subscribers: llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10381 llvm-svn: 239815
* [MachineSink] Address post-commit review commentsArnaud A. de Grandmaison2015-06-161-21/+28
| | | | | | | The successors cache is now a local variable, making it more visible that it is only valid for the MBB being processed. llvm-svn: 239807
* MIR Serialization: Print and parse simple machine function attributes.Alex Lorenz2015-06-162-0/+8
| | | | | | | | | | | This commit serializes the simple, scalar attributes from the 'MachineFunction' class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10449 llvm-svn: 239790
* MIR Serialization: move the MIR printer out of the MIR printing pass.Alex Lorenz2015-06-154-41/+110
| | | | | | | | | This commit decouples the MIR printer and the MIR printing pass so that it will be possible to move the MIR printer into a separate machine IR library later on. Reviewers: Duncan P. N. Exon Smith llvm-svn: 239788
* Debug Info IR: Switch DIObjCProperty to use DITypeRef.Adrian Prantl2015-06-151-1/+1
| | | | | | | | This is a prerequisite for turning on ODR type uniquing for ObjC++. rdar://problem/21377883 llvm-svn: 239780
* MIR Serialization: Create dummy functions when the MIR file doesn't have ↵Alex Lorenz2015-06-151-3/+24
| | | | | | | | | | | | | | | LLVM IR. This commit creates a dummy LLVM IR function with one basic block and an unreachable instruction for each parsed machine function when the MIR file doesn't have LLVM IR. This change is required as the machine function analysis pass creates machine functions only for the functions that are defined in the current LLVM module. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10135 llvm-svn: 239778
* MIR Serialization: Report an error when machine functions have the same name.Alex Lorenz2015-06-151-0/+3
| | | | | | | | | | | | This commit reports an error when the MIR parser encounters a machine function with the name that is the same as the name of a different machine function. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10130 llvm-svn: 239774
* Protection against stack-based memory corruption errors using SafeStackPeter Collingbourne2015-06-152-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the safe stack instrumentation pass to LLVM, which separates the program stack into a safe stack, which stores return addresses, register spills, and local variables that are statically verified to be accessed in a safe way, and the unsafe stack, which stores everything else. Such separation makes it much harder for an attacker to corrupt objects on the safe stack, including function pointers stored in spilled registers and return addresses. You can find more information about the safe stack, as well as other parts of or control-flow hijack protection technique in our OSDI paper on code-pointer integrity (http://dslab.epfl.ch/pubs/cpi.pdf) and our project website (http://levee.epfl.ch). The overhead of our implementation of the safe stack is very close to zero (0.01% on the Phoronix benchmarks). This is lower than the overhead of stack cookies, which are supported by LLVM and are commonly used today, yet the security guarantees of the safe stack are strictly stronger than stack cookies. In some cases, the safe stack improves performance due to better cache locality. Our current implementation of the safe stack is stable and robust, we used it to recompile multiple projects on Linux including Chromium, and we also recompiled the entire FreeBSD user-space system and more than 100 packages. We ran unit tests on the FreeBSD system and many of the packages and observed no errors caused by the safe stack. The safe stack is also fully binary compatible with non-instrumented code and can be applied to parts of a program selectively. This patch is our implementation of the safe stack on top of LLVM. The patches make the following changes: - Add the safestack function attribute, similar to the ssp, sspstrong and sspreq attributes. - Add the SafeStack instrumentation pass that applies the safe stack to all functions that have the safestack attribute. This pass moves all unsafe local variables to the unsafe stack with a separate stack pointer, whereas all safe variables remain on the regular stack that is managed by LLVM as usual. - Invoke the pass as the last stage before code generation (at the same time the existing cookie-based stack protector pass is invoked). - Add unit tests for the safe stack. Original patch by Volodymyr Kuznetsov and others at the Dependable Systems Lab at EPFL; updates and upstreaming by myself. Differential Revision: http://reviews.llvm.org/D6094 llvm-svn: 239761
* MIR Serialization: Connect the machine function analysis pass to the MIR parser.Alex Lorenz2015-06-154-33/+102
| | | | | | | | | | | | | | | | | | | | | This commit connects the machine function analysis pass (which creates machine functions) to the MIR parser, which will initialize the machine functions with the state from the MIR file and reconstruct the machine IR. This commit introduces a new interface called 'MachineFunctionInitializer', which can be used to provide custom initialization for the machine functions. This commit also introduces a new diagnostic class called 'DiagnosticInfoMIRParser' which is used for MIR parsing errors. This commit modifies the default diagnostic handling in LLVMContext - now the the diagnostics are printed directly into llvm::errs() so that the MIR parsing errors can be printed with colours. Reviewers: Justin Bogner Differential Revision: http://reviews.llvm.org/D9928 llvm-svn: 239753
* Unbreak the build from r239740.Sanjoy Das2015-06-151-4/+4
| | | | | | Do not re-use an enum name as a field name. Some bots don't like this. llvm-svn: 239746
* [CodeGen] Add a pass to fold null checks into nearby memory operations.Sanjoy Das2015-06-154-0/+270
| | | | | | | | | | | | | | | | | | | | | Summary: This change adds an "ImplicitNullChecks" target dependent pass. This pass folds null checks into memory operation using the FAULTING_LOAD pseudo-op introduced in previous patches. Depends on D10197 Depends on D10199 Depends on D10200 Reviewers: reames, rnk, pgavlin, JosephTremoulet, atrick Reviewed By: atrick Subscribers: ab, JosephTremoulet, llvm-commits Differential Revision: http://reviews.llvm.org/D10201 llvm-svn: 239743
* [TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.Sanjoy Das2015-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: TargetInstrInfo::getLdStBaseRegImmOfs to TargetInstrInfo::getMemOpBaseRegImmOfs and implement for x86. The implementation only handles a few easy cases now and will be made more sophisticated in the future. This is NFCI: the only user of `getLdStBaseRegImmOfs` (now `getmemOpBaseRegImmOfs`) is `LoadClusterMotion` and `LoadClusterMotion` is disabled for x86. Reviewers: reames, ab, MatzeB, atrick Reviewed By: MatzeB, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10199 llvm-svn: 239741
* [CodeGen] Introduce a FAULTING_LOAD_OP pseudo-op.Sanjoy Das2015-06-152-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This instruction encodes a loading operation that may fault, and a label to branch to if the load page-faults. The locations of potentially faulting loads and their "handler" destinations are recorded in a FaultMap section, meant to be consumed by LLVM's clients. Nothing generates FAULTING_LOAD_OP instructions yet, but they will be used in a future change. The documentation (FaultMaps.rst) needs improvement and I will update this diff with a more expanded version shortly. Depends on D10196 Reviewers: rnk, reames, AndyAyers, ab, atrick, pgavlin Reviewed By: atrick, pgavlin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10197 llvm-svn: 239740
* [MachineSink] Improve runtime performance. NFC.Arnaud A. de Grandmaison2015-06-151-35/+59
| | | | | | | | | | | | This patch fixes a compilation time issue, when MachineSink faces PHIs with a huge number of operands. This can happen for example in goto table based interpreters, where some basic blocks can have several of those PHIs, each one with several hundreds operands. MachineSink was spending a significant time re-building and re-sorting the list of successors of the current MachineBasicBlock. The computing and sorting of the current MachineBasicBlock successors is now cached. llvm-svn: 239720
* AsmPrinter.cpp: Avoid crashes for targeting like "arm-mingw32". CurrentFnSym ↵NAKAMURA Takumi2015-06-141-1/+2
| | | | | | might not be <MCSymbolELF> here. llvm-svn: 239692
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