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* Chain dependencies used to enforce memory order should have latency of 0 ↵David Goodwin2009-11-021-14/+23
| | | | | | (except for true dependency of Store followed by aliased Load... we estimate that case with a single cycle of latency assuming the hardware will bypass) llvm-svn: 85807
* Initilize the machine LICM CSE map upon the first time an instruction is ↵Evan Cheng2009-11-021-17/+46
| | | | | | | | | | hoisted to the loop preheader. Add instructions which are already in the preheader block that may be common expressions of those that are hoisted out. These does get a few more instructions CSE'ed. llvm-svn: 85799
* Add PseudoSourceValue::mayAlias. It returns true if the object can ever ↵Evan Cheng2009-11-011-0/+17
| | | | | | alias any LLVM IR value. llvm-svn: 85762
* Fix a missing newline in the dwarf output code.Dan Gohman2009-10-311-0/+1
| | | | llvm-svn: 85684
* Make -print-machineinstrs more readable.Dan Gohman2009-10-316-66/+97
| | | | | | | | | | | | | | - Be consistent when referring to MachineBasicBlocks: BB#0. - Be consistent when referring to virtual registers: %reg1024. - Be consistent when referring to unknown physical registers: %physreg10. - Be consistent when referring to known physical registers: %RAX - Be consistent when referring to register 0: %reg0 - Be consistent when printing alignments: align=16 - Print jump table contents. - Don't print host addresses, in general. - and various other cleanups. llvm-svn: 85682
* Factor out more code into addCommonCodeGenPasses. The JIT wasn'tDan Gohman2009-10-311-32/+30
| | | | | | | | previously running CodePlacementOpt. Also print headers before each dump in -print-machineinstrs mode, so that it's clear which dump is which. llvm-svn: 85681
* Remove CodeGenLICM. It's largely obsoleted by MachineLICM's new abilityDan Gohman2009-10-311-6/+1
| | | | | | to unfold loop-invariant loads. llvm-svn: 85657
* When discarding SrcValue information, discard all of it so that codeDan Gohman2009-10-311-7/+5
| | | | | | that uses this information knows to behave conservatively. llvm-svn: 85654
* Fix 80-column violation.Dan Gohman2009-10-311-1/+2
| | | | llvm-svn: 85653
* Fix warning with gcc-4.0 and signed/unsigned.Eric Christopher2009-10-311-1/+1
| | | | llvm-svn: 85648
* Add assertion checks here to turn silent miscompiles into aborts.Dan Gohman2009-10-301-4/+8
| | | | llvm-svn: 85639
* Don't mark registers dead here when processing nodes with MVT::FlagDan Gohman2009-10-301-1/+5
| | | | | | | results. This works around a problem affecting targets which rely on MVT::Flag to handle physical register defs. llvm-svn: 85638
* Fix MachineLICM to use the correct virtual register class whenDan Gohman2009-10-301-2/+4
| | | | | | | | | | unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the opcode of the original operation without the load, not the load itself, MachineLICM needs to know the operand index in order to get the correct register class. Extend getOpcodeAfterMemoryUnfold to return this information. llvm-svn: 85622
* Stop the iterator in ValueLiveAt from potentially running off the end of the ↵Lang Hames2009-10-302-4/+7
| | | | | | interval. llvm-svn: 85599
* Don't delete blocks which have their address taken.Dan Gohman2009-10-301-2/+3
| | | | llvm-svn: 85572
* Mention if a block has its address taken in debug output.Dan Gohman2009-10-301-0/+1
| | | | llvm-svn: 85571
* Add support for BlockAddress static initializers.Dan Gohman2009-10-301-0/+2
| | | | llvm-svn: 85562
* Add a FIXME comment.Dan Gohman2009-10-301-0/+2
| | | | llvm-svn: 85559
* Add some comments.Dan Gohman2009-10-301-0/+8
| | | | llvm-svn: 85558
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-307-3/+83
| | | | llvm-svn: 85556
* Between scheduling regions, correctly maintain anti-dep breaking state so ↵David Goodwin2009-10-291-5/+7
| | | | | | that we don't incorrectly rename registers that span these regions. llvm-svn: 85537
* Remove some unnecessary spaces in debug output.Dan Gohman2009-10-291-3/+3
| | | | llvm-svn: 85536
* Move some code from being emitted as boilerplate duplicated in everyDan Gohman2009-10-291-0/+52
| | | | | | *ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp. llvm-svn: 85530
* Fix a couple of bugs in aggressive anti-dep breaking.David Goodwin2009-10-292-36/+62
| | | | llvm-svn: 85522
* Refactor complicated predicate into a separate function.Bob Wilson2009-10-291-17/+33
| | | | llvm-svn: 85519
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-292-4/+8
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Refactor the code for unfolding a load into a separate function.Dan Gohman2009-10-291-50/+62
| | | | llvm-svn: 85515
* Reapply r85338.Bill Wendling2009-10-292-2/+22
| | | | llvm-svn: 85514
* When the function is doing dynamic stack realignment, the spill slot will beJim Grosbach2009-10-291-2/+2
| | | | | | | | indexed via the stack pointer, even if a frame pointer is present. Update the heuristic to place it nearest the stack pointer in that case, rather than nearest the frame pointer. llvm-svn: 85474
* When there is a 2-instruction spill sequence, recordDale Johannesen2009-10-291-2/+3
| | | | | | | | the second (store) instruction in SpillSlotToUsesMap consistently. I don't think this matters functionally, but it's cleaner and Evan wants it this way. llvm-svn: 85463
* Don't put in these EH changes.Bill Wendling2009-10-292-293/+37
| | | | llvm-svn: 85460
* Reverting r85338 for now. It's causing a bootstrap failure on PPC darwin9.Bill Wendling2009-10-294-59/+295
| | | | | | | | --- Reverse-merging r85338 into '.': U lib/CodeGen/SimpleRegisterCoalescing.cpp U lib/CodeGen/SimpleRegisterCoalescing.h llvm-svn: 85454
* Reimplement BranchFolding change to avoid tail merging for a 1 instructionBob Wilson2009-10-281-13/+15
| | | | | | | common tail, except when the OptimizeForSize function attribute is present. Radar 7338114. llvm-svn: 85441
* When we generate spill code, then decide we don't needDale Johannesen2009-10-281-1/+4
| | | | | | | | | | to spill after all, we weren't handling 2-instruction spill sequences correctly (PPC Altivec). We need to remove the store in this case. Removing the other instruction(s) would be goodness but is not needed for correctness, and isn't done here. 7331562. llvm-svn: 85437
* Make sure we return the right sized type here.Eric Christopher2009-10-281-2/+5
| | | | llvm-svn: 85436
* Revert r85346 change to control tail merging by CodeGenOpt::Level.Bob Wilson2009-10-284-24/+15
| | | | | | I'm going to redo this using the OptimizeForSize function attribute. llvm-svn: 85426
* Make AntiDepReg.h internal.David Goodwin2009-10-284-3/+65
| | | | llvm-svn: 85412
* Don't call SDNode::isPredecessorOf when it isn't necessary. If the load'sDan Gohman2009-10-281-6/+10
| | | | | | chains have no users, they can't be predecessors of the condition. llvm-svn: 85394
* Simplify this code: if the unfolded load can't be hoisted, just deleteDan Gohman2009-10-281-16/+3
| | | | | | the new instructions and leave the old one in place. llvm-svn: 85393
* Rewrite SelectionDAG::isPredecessorOf to be iterative instead ofDan Gohman2009-10-281-21/+16
| | | | | | | recursive to avoid consuming extraordinary amounts of stack space when processing tall graphs. llvm-svn: 85369
* Teach MachineLICM to unfold loads from constant memory fromDan Gohman2009-10-281-17/+83
| | | | | | | otherwise unhoistable instructions in order to allow the loads to be hoisted. llvm-svn: 85364
* Add a second ValueType argument to isFPImmLegal.Evan Cheng2009-10-281-1/+1
| | | | llvm-svn: 85361
* Mark dead physregdefs dead immediately. This helps MachineSink andDan Gohman2009-10-281-0/+2
| | | | | | MachineLICM and other things which run before LiveVariables is run. llvm-svn: 85360
* Allow constants of different types to share constant pool entriesDan Gohman2009-10-281-3/+47
| | | | | | if they have compatible encodings. llvm-svn: 85359
* rename indbr -> indirectbr to appease the residents of #llvm.Chris Lattner2009-10-282-3/+3
| | | | llvm-svn: 85351
* Record CodeGen optimization level in the BranchFolding pass so that we canBob Wilson2009-10-274-15/+24
| | | | | | | | | | | | | | | | use it to control tail merging when there is a tradeoff between performance and code size. When there is only 1 instruction in the common tail, we have been merging. That can be good for code size but is a definite loss for performance. Now we will avoid tail merging in that case when the optimization level is "Aggressive", i.e., "-O3". Radar 7338114. Since the IfConversion pass invokes BranchFolding, it too needs to know the optimization level. Note that I removed the RegisterPass instantiation for IfConversion because it required a default constructor. If someone wants to keep that for some reason, we can add a default constructor with a hard-wired optimization level. llvm-svn: 85346
* Fixed a bug in the coalescer where intervals were occasionally merged ↵Lang Hames2009-10-272-2/+22
| | | | | | despite a real interference. This fixes rdar://problem/7157961. llvm-svn: 85338
* Update the MachineBasicBlock CFG for an indirect branch.Dan Gohman2009-10-271-0/+4
| | | | llvm-svn: 85325
* Add CodeGen support for indirect branches.Dan Gohman2009-10-271-2/+3
| | | | llvm-svn: 85323
* Do not held on to DenseMap slot accross map insertion. The insertion may ↵Devang Patel2009-10-272-22/+26
| | | | | | | | cause the map to grow rending the slot invalid. Use this opportunity to use ValueMap instead of DenseMap. llvm-svn: 85298
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