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* Teach iff-converter to properly count # of dups. It was not skipping over ↵Evan Cheng2010-06-181-1/+27
| | | | | | dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384. llvm-svn: 106323
* Add Expand-to-libcall support for additional atomics. This covers the usualJim Grosbach2010-06-182-4/+152
| | | | | | | | | | entries used by llvm-gcc. *_[U]MIN and such can be added later if needed. This enables the front ends to simplify handling of the atomic intrinsics by removing the target-specific decision about which targets can handle the intrinsics. llvm-svn: 106321
* Don't leak RegClass2VRegMap, which is now a new[] array instead of aDan Gohman2010-06-181-0/+1
| | | | | | std::vector. llvm-svn: 106298
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-2/+2
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* Fix PR7372: Conditional branches (at least on ARM) are treated as predicated,Bob Wilson2010-06-181-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore an instruction because it is a branch, it should not check if the branch is predicated. This case (when IgnoreBr is true) is only relevant from IfConvertTriangle, where new branches are inserted after the block has been copied and predicated. If the original branch is not removed, we end up with multiple conditional branches (possibly conflicting) at the end of the block. Aside from any immediate errors resulting from that, this confuses the AnalyzeBranch functions so that the branches are not analyzable. That in turn causes the IfConverter to think that the "Simple" pattern can be applied, and things go downhill fast because the "Simple" pattern does _not_ apply if the block can fall through. This is pretty fragile. If there are other degenerate cases where AnalyzeBranch fails, but where the block may still fall through, the IfConverter should not perform its "Simple" if-conversion. But, I don't know how to do that with the current AnalyzeBranch interface, so for now, the best thing seems to be to avoid creating branches that AnalyzeBranch cannot handle. Evan, please review! llvm-svn: 106291
* Don't bother calling releaseMemory before destroying the DominatorTreeBase.Dan Gohman2010-06-181-1/+0
| | | | llvm-svn: 106287
* Minor code simplifications.Dan Gohman2010-06-181-18/+12
| | | | llvm-svn: 106286
* Give NamedRegionTimer an Enabled flag, allowing all its clients toDan Gohman2010-06-183-97/+47
| | | | | | | | | | | | | | | | | | | | switch from this: if (TimePassesIsEnabled) { NamedRegionTimer T(Name, GroupName); do_something(); } else { do_something(); // duplicate the code, this time without a timer! } to this: { NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled); do_something(); } llvm-svn: 106285
* Don't replace the old Ordering object with a new one; just clear()Dan Gohman2010-06-181-2/+1
| | | | | | the old one. llvm-svn: 106284
* Don't call clear() on DbgInfo when it's going to be deleted anyway.Dan Gohman2010-06-181-3/+0
| | | | | | | Don't replace the old DbgInfo with a new one when clear() on the old one is sufficient. llvm-svn: 106283
* Change UpdateNodeOperands' operand and return value from SDValue toDan Gohman2010-06-187-84/+97
| | | | | | SDNode *, since it doesn't care about the ResNo value. llvm-svn: 106282
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-183-4/+4
| | | | llvm-svn: 106279
* isValueValidForType can be a static member function.Dan Gohman2010-06-181-1/+1
| | | | llvm-svn: 106278
* Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,Dan Gohman2010-06-184-111/+50
| | | | | | which is faster, simpler, and less surprising. llvm-svn: 106263
* Handle ext(ext(x)) -> ext(x) immediately, since it's simple.Dan Gohman2010-06-181-1/+2
| | | | llvm-svn: 106256
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-175-26/+36
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* add missing break. inconsequential as the code shouldn't be reached, butJim Grosbach2010-06-171-0/+1
| | | | | | for correctness' sake, it should be there. llvm-svn: 106229
* Add entries for Expanding atomic intrinsics to libcalls. Just a placeholderJim Grosbach2010-06-171-0/+19
| | | | | | | | | | | | | | for the moment. The implementation of the libcall will follow. Currently, the llvm-gcc knows when the intrinsics can be correctly handled by the back end and only generates them in those cases, issuing libcalls directly otherwise. That's too much coupling. The intrinsics should always be generated and the back end decide how to handle them, be it with a libcall, inline code, or whatever. This patch is a step in that direction. rdar://8097623 llvm-svn: 106227
* ISD::MEMBARRIER should lower to a libcall (__sync_synchronize) if the targetJim Grosbach2010-06-171-1/+13
| | | | | | sets the legalize action to Expand. llvm-svn: 106203
* Allow a register to be redefined multiple times in a basic block.Jakob Stoklund Olesen2010-06-161-6/+2
| | | | | | | | | | | | | | | | | | | | LiveVariableAnalysis was a bit picky about a register only being redefined once, but that really isn't necessary. Here is an example of chained INSERT_SUBREGs that we can handle now: 68 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14 register: %reg1040 +[70,134:0) 76 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13 register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0) 0@78-(134) 1@70-(78) 84 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12 register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0) 0@86-(134) 1@70-(78) 2@78-(86) 92 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11 register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0) 0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94) rdar://problem/8096390 llvm-svn: 106152
* add FIXMEJim Grosbach2010-06-161-0/+3
| | | | llvm-svn: 106126
* Improve comment to include that the use of a preg is also verboten in this ↵Bill Wendling2010-06-161-3/+4
| | | | | | situation. llvm-svn: 106119
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-167-91/+254
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. llvm-svn: 106091
* Use separate named MDNode to hold each function's local variable info.Devang Patel2010-06-161-2/+3
| | | | | | This speeds up local variable handling in DwarfDebug. llvm-svn: 106075
* Don't emit the linkage for initializer label for mach-o tls.Eric Christopher2010-06-161-1/+0
| | | | llvm-svn: 106073
* Create a more targeted fix for not sinking instructions into a range where itBill Wendling2010-06-151-50/+10
| | | | | | | | will conflict with another live range. The place which creates this scenerio is the code in X86 that lowers a select instruction by splitting the MBBs. This eliminates the need to check from the bottom up in an MBB for live pregs. llvm-svn: 106066
* Added a comment.Stuart Hastings2010-06-151-0/+5
| | | | llvm-svn: 106063
* Fix 80col violations, remove trailing whitespace, and clarify a comment.Bob Wilson2010-06-151-14/+15
| | | | llvm-svn: 106057
* Remove the local register allocator.Jakob Stoklund Olesen2010-06-152-1255/+0
| | | | | | Please use the fast allocator instead. llvm-svn: 106051
* Fixed vector widening of binary instructions that can trap. Patch by Visa ↵Mon P Wang2010-06-151-27/+71
| | | | | | Putkinen! llvm-svn: 106038
* IfConversion's AnalyzeBlocks method always returns false; clean it up.Bob Wilson2010-06-151-9/+5
| | | | llvm-svn: 106027
* fix namingJim Grosbach2010-06-151-3/+3
| | | | llvm-svn: 106024
* Fix an exotic bug that only showed up in an internal test case.Jakob Stoklund Olesen2010-06-151-2/+4
| | | | | | | | SimpleRegisterCoalescing::JoinIntervals() uses CoalescerPair to determine if a copy is coalescable, and in very rare cases it can return true where LHS is not live - the coalescable copy can come from an alias of the physreg in LHS. llvm-svn: 106021
* Fix a comment typo.Bob Wilson2010-06-151-1/+1
| | | | llvm-svn: 106015
* Add some missing checks for the case where the extract_subregs areBob Wilson2010-06-151-22/+23
| | | | | | | | combined to an insert_subreg, i.e., where the destination register is larger than the source. We need to check that the subregs can be composed for that case in a symmetrical way to the case when the destination is smaller. llvm-svn: 106004
* Avoid processing early clobbers twice in RegAllocFast.Jakob Stoklund Olesen2010-06-151-3/+8
| | | | | | | | | Early clobbers defining a virtual register were first alocated to a physreg and then processed as a physreg EC, spilling the virtreg. This fixes PR7382. llvm-svn: 105998
* Add CoalescerPair helper class.Jakob Stoklund Olesen2010-06-153-40/+174
| | | | | | | | | | | | | | | | | | | | Given a copy instruction, CoalescerPair can determine which registers to coalesce in order to eliminate the copy. It deals with all the subreg fun to determine a tuple (DstReg, SrcReg, SubIdx) such that: - SrcReg is a virtual register that will disappear after coalescing. - DstReg is a virtual or physical register whose live range will be extended. - SubIdx is 0 when DstReg is a physical register. - SrcReg can be joined with DstReg:SubIdx. CoalescerPair::isCoalescable() determines if another copy instruction is compatible with the same tuple. This fixes some NEON miscompilations where shuffles are getting coalesced as if they were copies. The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy later. llvm-svn: 105997
* Generalize the pre-coalescing of extract_subregs feeding reg_sequences,Bob Wilson2010-06-151-33/+83
| | | | | | | | | replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. llvm-svn: 105991
* Update CMake build.Ted Kremenek2010-06-151-2/+2
| | | | llvm-svn: 105987
* More dbg_value cleanup so the presence of debug info doesn't affect code-gen.Jim Grosbach2010-06-141-2/+21
| | | | | | | Make sure to skip the dbg_value instructions when moving dups out of the diamond. rdar://7797940 llvm-svn: 105965
* - Do away with SimpleHazardRecognizer.h. It's not used and offers little value.Evan Cheng2010-06-145-225/+20
| | | | | | - Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it. llvm-svn: 105959
* Avoid uncessary array copying.Evan Cheng2010-06-141-7/+19
| | | | llvm-svn: 105955
* fix a -Wbool-conversions warning from clang.Chris Lattner2010-06-141-1/+1
| | | | llvm-svn: 105942
* When performing the Horrible Hack(tm-Duncan) on the EH code to convert aBill Wendling2010-06-121-26/+49
| | | | | | | | clean-up to a catch-all after inlining, take into account that there could be filter IDs as well. The presence of filters don't mean that the selector catches anything. It's just metadata information. llvm-svn: 105872
* Allow target to provide its own hazard recognizer to post-ra scheduler.Evan Cheng2010-06-121-6/+16
| | | | llvm-svn: 105862
* Code formatting.Evan Cheng2010-06-121-5/+3
| | | | llvm-svn: 105861
* Support for nested functions/classes in debug output. (Again.) Radar 7424645.Stuart Hastings2010-06-111-1/+23
| | | | llvm-svn: 105828
* Code refactoring, no functionality changes.Evan Cheng2010-06-102-83/+87
| | | | llvm-svn: 105775
* Mark physregs defined by inline asm as implicit.Jakob Stoklund Olesen2010-06-091-2/+6
| | | | | | | This is a bit of a hack to make inline asm look more like call instructions. It would be better to produce correct dead flags during isel. llvm-svn: 105749
* Allow target to place 2-address pass inserted copies in better spots. Thumb2 ↵Evan Cheng2010-06-091-1/+6
| | | | | | will use this to try to avoid breaking up IT blocks. llvm-svn: 105745
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