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* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-023-50/+50
| | | | llvm-svn: 202621
* Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.Craig Topper2014-03-021-1/+1
| | | | llvm-svn: 202618
* [C++11] Switch all uses of the llvm_move macro to use std::moveChandler Carruth2014-03-021-3/+3
| | | | | | directly, and remove the macro. llvm-svn: 202612
* [C++11] Expand and eliminate the LLVM_ENUM_INT_TYPE() macroAlp Toker2014-03-022-2/+2
| | | | llvm-svn: 202607
* Make helper function static.Benjamin Kramer2014-03-011-2/+1
| | | | llvm-svn: 202596
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-014-65/+26
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* SpillPlacement: fix a bug in iterate.Manman Ren2014-02-281-2/+4
| | | | | | | | | | | Inside iterate, we scan backwards then scan forwards in a loop. When iteration is not zero, the last node was just updated so we can skip it. But when iteration is zero, we can't skip the last node. For the testing case, fixing this will save a spill and move register copies from hot path to cold path. llvm-svn: 202557
* Jumped the gun with r202551 and broke some bots that weren't yet C++11ified.Lang Hames2014-02-281-38/+38
| | | | | | Reverting until the C++11 switch is complete. llvm-svn: 202554
* New PBQP solver, and updates to the PBQP graph.Lang Hames2014-02-281-38/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous PBQP solver was very robust but consumed a lot of memory, performed a lot of redundant computation, and contained some unnecessarily tight coupling that prevented experimentation with novel solution techniques. This new solver is an attempt to address these shortcomings. Important/interesting changes: 1) The domain-independent PBQP solver class, HeuristicSolverImpl, is gone. It is replaced by a register allocation specific solver, PBQP::RegAlloc::Solver (see RegAllocSolver.h). The optimal reduction rules and the backpropagation algorithm have been extracted into stand-alone functions (see ReductionRules.h), which can be used to build domain specific PBQP solvers. This provides many more opportunities for domain-specific knowledge to inform the PBQP solvers' decisions. In theory this should allow us to generate better solutions. In practice, we can at least test out ideas now. As a side benefit, I believe the new solver is more readable than the old one. 2) The solver type is now a template parameter of the PBQP graph. This allows the graph to notify the solver of any modifications made (e.g. by domain independent rules) without the overhead of a virtual call. It also allows the solver to supply policy information to the graph (see below). 3) Significantly reduced memory overhead. Memory management policy is now an explicit property of the PBQP graph (via the CostAllocator typedef on the graph's solver template argument). Because PBQP graphs for register allocation tend to contain many redundant instances of single values (E.g. the value representing an interference constraint between GPRs), the new RASolver class uses a uniquing scheme. This massively reduces memory consumption for large register allocation problems. For example, looking at the largest interference graph in each of the SPEC2006 benchmarks (the largest graph will always set the memory consumption high-water mark for PBQP), the average memory reduction for the PBQP costs was 400x. That's times, not percent. The highest was 1400x. Yikes. So - this is fixed. "PBQP: No longer feasting upon every last byte of your RAM". Minor details: - Fully C++11'd. Never copy-construct another vector/matrix! - Cute tricks with cost metadata: Metadata that is derived solely from cost matrices/vectors is attached directly to the cost instances themselves. That way if you unique the costs you never have to recompute the metadata. 400x less memory means 400x less cost metadata (re)computation. Special thanks to Arnaud de Grandmaison, who has been the source of much encouragement, and of many very useful test cases. This new solver forms the basis for future work, of which there's plenty to do. I will be adding TODO notes shortly. - Lang. llvm-svn: 202551
* Fix visitTRUNCATE for legal i1 valuesHal Finkel2014-02-281-1/+1
| | | | | | | | | | | This extract-and-trunc vector optimization cannot work for i1 values as currently implemented, and so I'm disabling this for now for i1 values. In the future, this can be fixed properly. Soon I'll commit support for i1 CR bit tracking in the PowerPC backend, and this will be covered by one of the existing regression tests. llvm-svn: 202449
* Provide a target override for the latest regalloc heuristic.Andrew Trick2014-02-271-1/+1
| | | | | | | This is a temporary workaround for native arm linux builds: PR18996: Changing regalloc order breaks "lencod" on native arm linux builds. llvm-svn: 202433
* Revert r201751 and solve the const problem a different way - byEric Christopher2014-02-273-28/+16
| | | | | | making the cache mutable. llvm-svn: 202417
* Debug info: Remove ARMAsmPrinter::EmitDwarfRegOp(). AsmPrinter can nowAdrian Prantl2014-02-271-34/+83
| | | | | | | | | | scan the register file for sub- and super-registers. No functionality change intended. (Tests are updated because the comments in the assembler output are different.) llvm-svn: 202416
* Don't emit anything into the debug_ranges section if we aren't emittingEric Christopher2014-02-271-1/+1
| | | | | | | | | | any ranges - this includes CU ranges where we were previously emitting an end list marker even if we didn't have a list. Testcase includes a test for line table only code emission as the problem was noticed while writing this test. llvm-svn: 202357
* If we're only emitting line tables for a particular CU then don't addEric Christopher2014-02-271-1/+6
| | | | | | | | | | | any ranges to the list of ranges for the CU as we don't want to emit them anyway. This ensures that we will still emit ranges if we have a compile unit compiled with only line tables and one compiled with full debug info requested (we'll emit for the one with full debug info). Update testcase metadata accordingly to continue emitting ranges. llvm-svn: 202333
* Fix a type error that crept into r202313.Adrian Prantl2014-02-261-1/+1
| | | | llvm-svn: 202317
* Remove unnecessary llvm:: qualification.Eric Christopher2014-02-261-1/+1
| | | | llvm-svn: 202316
* Debug info: Refactor AsmPrinter::EmitDwarfRegOp to make the control flowAdrian Prantl2014-02-261-60/+90
| | | | | | more obvious. llvm-svn: 202313
* Add a limit to the heuristic that register allocates instructions in local ↵Andrew Trick2014-02-261-2/+8
| | | | | | | | | | | | order. This handles pathological cases in which we see 2x increase in spill code for large blocks (~50k instructions). I don't have a unit test for this behavior. Fixes rdar://16072279. llvm-svn: 202304
* Fix the aggressive anti-dep breaker's subregister definition handlingHal Finkel2014-02-261-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The aggressive anti-dependency breaker scans instructions, bottom-up, within the scheduling region in order to find opportunities where register renaming can be used to break anti-dependencies. Unfortunately, the aggressive anti-dep breaker was treating a register definition as defining all of that register's aliases (including super registers). This behavior is incorrect when the super register is live and there are other definitions of subregisters of the super register. For example, given the following sequence: %CR2EQ<def> = CROR %CR3UN, %CR3UN<kill> %CR2GT<def> = IMPLICIT_DEF %X4<def> = MFOCRF8 %CR2 the analysis of the first subregister definition would work as expected: Anti: %CR2GT<def> = IMPLICIT_DEF Def Groups: CR2GT=g194->g0(via CR2) Antidep reg: CR2GT (zero group) Use Groups: but the analysis of the second one would not: Anti: %CR2EQ<def> = CROR %CR3UN, %CR3UN<kill> Def Groups: CR2EQ=g195 Antidep reg: CR2EQ Rename Candidates for Group g195: ... because, when processing the %CR2GT<def>, we'd mark all super registers of %CR2GT (%CR2 in this case) as defined. As a result, when processing %CR2EQ<def>, %CR2 no longer appears to be live, and %CR2EQ<def>'s group is not %unioned with the %CR2 group. I don't have an in-tree test case for this yet (and even if I did, I don't have a small one). llvm-svn: 202294
* 80-col.Eric Christopher2014-02-261-1/+2
| | | | llvm-svn: 202221
* Formatting fixups.Eric Christopher2014-02-261-2/+2
| | | | llvm-svn: 202220
* DwarfDebug: Avoid emitting an empty debug_aranges section when aranges are ↵David Blaikie2014-02-251-1/+2
| | | | | | disabled llvm-svn: 202201
* Address review comments for r202188.Adrian Prantl2014-02-253-32/+16
| | | | | | | | | This is refactoring / simplifying code, updating comments and enabling the testcase on non-x86 platforms. No functionality change. llvm-svn: 202199
* Debug info: Support variadic functions.Adrian Prantl2014-02-253-28/+50
| | | | | | | | | | | | | | Variadic functions have an unspecified parameter tag after the last argument. In IR this is represented as an unspecified parameter in the subroutine type. Paired commit with CFE r202185. rdar://problem/13690847 This re-applies r202184 + a bugfix in DwarfDebug's argument handling. llvm-svn: 202188
* Revert "Debug info: Support variadic functions."Adrian Prantl2014-02-253-37/+21
| | | | | | This reverts commit r202184 because of buildbot breakage. llvm-svn: 202187
* Remove outdated comments.Manman Ren2014-02-251-1/+1
| | | | llvm-svn: 202186
* Debug info: Support variadic functions.Adrian Prantl2014-02-253-21/+37
| | | | | | | | | | | | Variadic functions have an unspecified parameter tag after the last argument. In IR this is represented as an unspecified parameter in the subroutine type. Paired commit with CFE. rdar://problem/13690847 llvm-svn: 202184
* Keep the link register for uwtable.Logan Chien2014-02-251-3/+12
| | | | | | | | | | | The function with uwtable attribute might be visited by the stack unwinder, thus the link register should be considered as clobbered after the execution of the branch and link instruction (i.e. the definition of the machine instruction can't be ignored) even when the callee function are marked with noreturn. llvm-svn: 202165
* Fix typosAlp Toker2014-02-251-1/+1
| | | | llvm-svn: 202107
* Indent this continued line.Nick Lewycky2014-02-251-4/+4
| | | | llvm-svn: 202096
* Add missing constMatt Arsenault2014-02-241-1/+1
| | | | llvm-svn: 202074
* Trivial code simplificationMatt Arsenault2014-02-241-2/+1
| | | | llvm-svn: 202073
* Replace the F_Binary flag with a F_Text one.Rafael Espindola2014-02-242-2/+3
| | | | | | | | | After this I will set the default back to F_None. The advantage is that before this patch forgetting to set F_Binary would corrupt a file on windows. Forgetting to set F_Text produces one that cannot be read in notepad, which is a better failure mode :-) llvm-svn: 202052
* Don't make F_None the default.Rafael Espindola2014-02-241-1/+1
| | | | | | This will make it easier to switch the default to being binary files. llvm-svn: 202042
* LocalStackSlotAllocation: Turn one-iteration loop into if.Benjamin Kramer2014-02-231-12/+5
| | | | | | No functionality change. llvm-svn: 201974
* Fix typoManman Ren2014-02-221-1/+1
| | | | llvm-svn: 201944
* Move get[S|U]LEB128Size() to LEB128.h.Logan Chien2014-02-223-20/+20
| | | | | | | | | | This commit moves getSLEB128Size() and getULEB128Size() from MCAsmInfo to LEB128.h and removes some copy-and-paste code. Besides, this commit also adds some unit tests for the LEB128 functions. llvm-svn: 201937
* [CodeGenPrepare] Fix the check of the legality of an instruction.Quentin Colombet2014-02-221-1/+6
| | | | | | | | | The API expects an ISD opcode, not an IR opcode. Fixes a regression for R600. Related to <rdar://problem/15519855>. llvm-svn: 201923
* [CodeGenPrepare] Move CodeGenPrepare into lib/CodeGen.Quentin Colombet2014-02-223-0/+2916
| | | | | | | | | | | | CodeGenPrepare uses extensively TargetLowering which is part of libLLVMCodeGen. This is a layer violation which would introduce eventually a dependence on CodeGen in ScalarOpts. Move CodeGenPrepare into libLLVMCodeGen to avoid that. Follow-up of <rdar://problem/15519855> llvm-svn: 201912
* [DAGCombiner] PCMP* sets its result to all ones or zeros so we can AND with theQuentin Colombet2014-02-211-0/+18
| | | | | | | | | | | | | | shifted mask rather than masking and shifting separately. The patch adds this transformation to the DAGCombiner:   (shl (and (setcc:i8v16 ...) N01C) N1C) -> (and (setcc:i8v16 ...) N01C<<N1C) <rdar://problem/16054492> Patch by Adam Nemet <anemet@apple.com> llvm-svn: 201906
* [Stackmaps] Move the target-independent frame index elimination for ↵Juergen Ributzka2014-02-211-9/+6
| | | | | | | | | | | | stackmaps and patchpoints into target-specific code. The lowering of the frame index for stackmaps and patchpoints requires some target-specific magic and should therefore be handled in the target-specific eliminateFrameIndex method. This is related to <rdar://problem/16106219> llvm-svn: 201904
* DebugInfo: Remove the empty macinfo section.David Blaikie2014-02-211-3/+0
| | | | | | | | | | | We were just emitting a label for this section for no real reason - this caused us to emit the section even though we never put anything in it. Not bothering with a test (though not adamantly anti-test) because it seems somewhat arbitrary to test for the absence of this section anymore than the absence of any other section. llvm-svn: 201876
* Rename a few more DataLayout variables from TD to DL.Rafael Espindola2014-02-212-15/+15
| | | | llvm-svn: 201870
* Make DisableIntegratedAS a TargetOption.Rafael Espindola2014-02-211-5/+1
| | | | | | | This replaces the old NoIntegratedAssembler with at TargetOption. This is more flexible and will be used to forward clang's -no-integrated-as option. llvm-svn: 201836
* Fix change in behaviour accidentally introduced in r201754.Nick Lewycky2014-02-201-2/+4
| | | | llvm-svn: 201758
* Simplify the implementation of getUnderlyingObjectsForInstr, without ↵Nick Lewycky2014-02-201-13/+12
| | | | | | intending to change the semantics at all. llvm-svn: 201754
* Add support for hashing attributes with DW_FORM_block. This requiredEric Christopher2014-02-203-1/+35
| | | | | | | | | | | | | passing down an AsmPrinter instance so we could compute the size of the block which could be target specific. All of the test cases in the unittest don't have any target specific data so we can use a NULL AsmPrinter there. This also depends upon block data being added as integers. We can now hash the entire fission-cu.ll compile unit so turn the flag on there with the hash value. llvm-svn: 201752
* Make DIELoc/DIEBlock's ComputeSize method const. Add a setSizeEric Christopher2014-02-203-18/+30
| | | | | | | method to actually set it in the class to avoid computing it multiple times. llvm-svn: 201751
* Format.Eric Christopher2014-02-201-50/+50
| | | | llvm-svn: 201750
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