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* Fix batch of converting RegisterPass<> to INTIALIZE_PASS().Owen Anderson2010-07-211-2/+1
| | | | llvm-svn: 109045
* Use the right floating point load/store instructions in ↵Jakob Stoklund Olesen2010-02-261-2/+4
| | | | | | | | | | | | | | | | | | PPCInstrInfo::foldMemoryOperandImpl(). The PowerPC floating point registers can represent both f32 and f64 via the two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to allow cross-class coalescing. This coalescing only affects whether registers are spilled as f32 or f64. Spill slots must be accessed with load/store instructions corresponding to the class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking at the instruction opcode which is wrong. X86 has similar floating point register classes, but doesn't try to fold memory operands, so there is no problem there. llvm-svn: 97262
* Fix "the the" and similar typos.Dan Gohman2010-02-101-1/+1
| | | | llvm-svn: 95781
* Change errs() to dbgs().David Greene2010-01-051-1/+1
| | | | llvm-svn: 92587
* Add a bool flag to StackObjects telling whether they reference spillDavid Greene2009-11-121-4/+4
| | | | | | | | | | | | | slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. llvm-svn: 87022
* The Indexes Patch.Lang Hames2009-11-031-1/+1
| | | | | | | | | | | | | | | | This introduces a new pass, SlotIndexes, which is responsible for numbering instructions for register allocation (and other clients). SlotIndexes numbering is designed to match the existing scheme, so this patch should not cause any changes in the generated code. For consistency, and to avoid naming confusion, LiveIndex has been renamed SlotIndex. The processImplicitDefs method of the LiveIntervals analysis has been moved into its own pass so that it can be run prior to SlotIndexes. This was necessary to match the existing numbering scheme. llvm-svn: 85979
* Distinquish stack slots from other stack objects. They (and fixed objects) ↵Evan Cheng2009-10-171-2/+2
| | | | | | get FixedStack PseudoSourceValues. llvm-svn: 84326
* remove some uses of llvm/Support/Streams.hChris Lattner2009-08-231-6/+1
| | | | llvm-svn: 79842
* Move more to raw_ostream, provide support for writing MachineBasicBlock,Daniel Dunbar2009-07-241-0/+6
| | | | | | LiveInterval, etc to raw_ostream. llvm-svn: 76965
* Part 1.Evan Cheng2009-06-151-30/+9
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-141-2/+35
| | | | | | MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
* Make sure to color with only allocatable registers for the specific register ↵Evan Cheng2009-05-041-0/+9
| | | | | | class. llvm-svn: 70821
* In some rare cases, the register allocator can spill registers but end up ↵Evan Cheng2009-05-031-0/+36
| | | | | | | | | | not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants. Not yet enabled. This is part 1. More coming. llvm-svn: 70787
* Oy! When reverting r68073, I added in experimental code. Sorry...Bill Wendling2009-03-311-22/+1
| | | | llvm-svn: 68099
* Revert r68073. It's causing a failure in the Apple-style builds.Bill Wendling2009-03-311-1/+22
| | | | llvm-svn: 68092
* Add newlines at end of file (this can annoy gcov)Daniel Dunbar2009-03-141-1/+1
| | | | llvm-svn: 67000
* Convert VirtRegMap to a MachineFunctionPass.Owen Anderson2009-03-131-18/+40
| | | | llvm-svn: 66870
* Reorganization: Move the Spiller out of VirtRegMap.cpp into its own files. ↵Owen Anderson2009-03-111-1873/+2
| | | | | | No (intended) functionality change. llvm-svn: 66720
* Yet another case where the spiller marked two uses of the same register on ↵Evan Cheng2009-03-091-19/+10
| | | | | | the same instruction as kill. This fixes PR3706. llvm-svn: 66428
* If a MI uses the same register more than once, only mark one of them as 'kill'.Evan Cheng2009-03-081-6/+22
| | | | llvm-svn: 66363
* Last commit accidentially deleted this code.Evan Cheng2009-02-281-0/+4
| | | | llvm-svn: 65679
* The last commit was overly conservative. It's ok to reuse value that's ↵Evan Cheng2009-02-261-7/+0
| | | | | | already marked livein. llvm-svn: 65498
* If an available register falls through to a succ block, unset the last kill. ↵Evan Cheng2009-02-261-37/+76
| | | | | | Sorry, it's impossible to reduce a sensible test case. It basically requires the moon and stars to align in order to cause a failure. llvm-svn: 65497
* A couple of places where reused use operands should be marked kill. This is ↵Evan Cheng2009-02-171-0/+11
| | | | | | exposed by recent availability fallthrough changes. llvm-svn: 64745
* Revert this. It was breaking stuff.Bill Wendling2009-02-131-1/+1
| | | | llvm-svn: 64428
* Turn off the old way of handling debug information in the code generator. UseBill Wendling2009-02-131-1/+1
| | | | | | | the new way, where all of the information is passed on SDNodes and machine instructions. llvm-svn: 64427
* Adjust the sizes for a few SmallVectors to reflect their usage.Dan Gohman2009-02-121-2/+2
| | | | llvm-svn: 64381
* It's (currently) not safe to keep certain physical registers live across ↵Evan Cheng2009-02-121-2/+12
| | | | | | basic blocks, e.g. x86 fp stack registers. llvm-svn: 64374
* If availability info is kept when fallthrough into a bb, add the available ↵Evan Cheng2009-02-121-3/+21
| | | | | | registers to live-in set. llvm-svn: 64372
* Remove a bogus assertion. It's possible a live-in available value is used by ↵Evan Cheng2009-02-111-2/+0
| | | | | | a previous instruction. llvm-svn: 64339
* Implement PR3495: local spiller optimization. The local spiller can now keep ↵Evan Cheng2009-02-111-91/+208
| | | | | | availability information over BB boundaries. It visits BB's in depth first order. After visiting a BB if it find a successor which has a single predecessor it visits the successor next without clearing the availability information. This allows the successor to omit reloads or change them into copies. llvm-svn: 64298
* Explicitly pass in debug location information to BuildMI.Bill Wendling2009-02-031-1/+2
| | | | llvm-svn: 63599
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-4/+4
| | | | | | sub-register indices as well. llvm-svn: 62600
* Fix PR3124: overly strict assert.Evan Cheng2008-12-021-2/+4
| | | | llvm-svn: 60392
* Fix PR2898. Spiller delete a store for reuse before it knows for sure the ↵Evan Cheng2008-10-171-11/+26
| | | | | | | | reuse happened. Patch by Lang Hames! llvm-svn: 57720
* Fix a very subtle spiller bug: UpdateKills should not forget to track defs ↵Evan Cheng2008-10-171-8/+14
| | | | | | of aliases. llvm-svn: 57673
* Fix command-line option printing to print two spaces where needed,Dan Gohman2008-10-141-2/+2
| | | | | | | | | instead of requiring all "short description" strings to begin with two spaces. This makes these strings less mysterious, and it fixes some cases where short description strings mistakenly did not begin with two spaces. llvm-svn: 57521
* Don't dereference the end() iterator. Thanks toDan Gohman2008-10-061-1/+1
| | | | | | ENABLE_EXPENSIVE_CHECKS for finding this. llvm-svn: 57181
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-14/+14
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Propagate subreg index when promoting a load to a copy.Evan Cheng2008-09-111-0/+7
| | | | llvm-svn: 56085
* Fix PR2664 - spiller GetRegForReload wasn't respecting sub-register indices ↵Evan Cheng2008-09-101-2/+4
| | | | | | on machine operands. llvm-svn: 56065
* Fix an overly strict assertion. Source register of a copy may not be killed, ↵Evan Cheng2008-09-041-1/+2
| | | | | | it may be killed by an implicit super-register use. llvm-svn: 55762
* Make SimpleSpiller respect subregister indices.Owen Anderson2008-08-191-2/+5
| | | | llvm-svn: 54968
* Fix PR2596: out of bound reference.Evan Cheng2008-08-051-3/+8
| | | | llvm-svn: 54375
* Fix a LocalSpiller leak. This fixes tramp3d-v4.Dan Gohman2008-07-181-0/+1
| | | | llvm-svn: 53766
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-6/+7
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* Cosmetic.Evan Cheng2008-06-181-1/+1
| | | | llvm-svn: 52450
* Fix read after free found by valgrind.Evan Cheng2008-06-161-15/+10
| | | | llvm-svn: 52309
* Teach the spiller to commute instructions in order to fold a reload. This ↵Evan Cheng2008-06-131-18/+125
| | | | | | hits 410 times on 444.namd and 122 times on 252.eon. llvm-svn: 52266
* Move #include to right place.Evan Cheng2008-06-041-0/+1
| | | | llvm-svn: 51932
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