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* Skip tied operand pairs that already have the same register.Jakob Stoklund Olesen2012-08-071-10/+11
| | | | llvm-svn: 161454
* Delete a dead variable.Jakob Stoklund Olesen2012-08-041-12/+0
| | | | | | TwoAddressInstructionPass doesn't remat any more. llvm-svn: 161285
* TwoAddressInstructionPass refactoring: Extract another method.Jakob Stoklund Olesen2012-08-031-121/+134
| | | | llvm-svn: 161284
* TwoAddressInstructionPass refactoring: Extract a method.Jakob Stoklund Olesen2012-08-031-48/+60
| | | | | | | No functional change intended, except replacing a DenseMap with a SmallDenseMap which should behave identically. llvm-svn: 161281
* Begin adding support for updating LiveIntervals in TwoAddressInstructionPass.Jakob Stoklund Olesen2012-08-031-0/+23
| | | | | | | This is far from complete, and only changes behavior when the -early-live-intervals flag is passed to llc. llvm-svn: 161273
* Delete dead function.Jakob Stoklund Olesen2012-08-031-28/+0
| | | | llvm-svn: 161242
* Don't delete dead code in TwoAddressInstructionPass.Jakob Stoklund Olesen2012-08-031-104/+0
| | | | | | | This functionality was added before we started running DeadMachineInstructionElim on all targets. It serves no purpose now. llvm-svn: 161241
* Disable rematerialization in TwoAddressInstructionPass.Manman Ren2012-07-251-78/+6
| | | | | | | | | | | It is redundant; RegisterCoalescer will do the remat if it can't eliminate the copy. Collected instruction counts before and after this. A few extra instructions are generated due to spilling but it is normal to see these kinds of changes with almost any small codegen change, according to Jakob. This also fixed rdar://11830760 where xor is expected instead of movi0. llvm-svn: 160749
* Fix a somewhat nasty crasher in PR13378. This crashes inside ofChandler Carruth2012-07-181-22/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LiveIntervals due to the two-addr pass generating bogus MI code. The crux of the issue was a loop nesting problem. The intent of the code which attempts to transform instructions before converting them to two-addr form is to defer and reprocess any transformed instructions as the second processing is likely to have more opportunities to coalesce copies, etc. Unfortunately, there was one section of processing that was not deferred -- the INSERT_SUBREG rewriting. Due to quirks of how this rewriting proceeded, not only did it occur early, it removed the bits of information needed for the deferred processing to correctly generate the necessary two address form (specifically inserting a copy), but didn't trigger any immediate assertions and produced what appeared to be already valid two-address from code. Thus, the assertion only fired much later in the pipeline. The fix is to hoist the transformation logic up layer to where it can more firmly defer all further processing, and to teach the normal processing to handle an edge case previously handled as part of the transformation logic. This edge case (already matched tied register operands) needs to *not* defer any steps. As has been brought up repeatedly in the process: wow does this code need refactoring. I *may* squeeze in some time to at least bring sanity to this loop... but wow... =] Thanks to Jakob for helpful hints on the way here, and the review. llvm-svn: 160443
* Add some trace output to TwoAddressInstructionPass.Jakob Stoklund Olesen2012-07-171-1/+4
| | | | llvm-svn: 160380
* Reapply r160194, switching to use LV information for finding local kills.Chandler Carruth2012-07-151-56/+32
| | | | | | | | | | | | | | | | | | | | | The notable fix is to look at any dependencies attached to the kill instruction (or other instructions between MI nad the kill) where the dependencies are specific to the register in question. The old code implicitly handled this by rejecting the transform if *any* other uses were found within the block, but after the start point. The new code directly finds the kill, and has to re-use the existing dependency scan to check for non-kill uses. This was caught by self-host, but I found the bug via inspection and use of absurd assert scaffolding to compute the kills in two ways and compare them. So I have no useful testcase for this other than "bootstrap". I'd work harder to reduce a test case if this particular code were likely to live for a long time. Thanks to Benjamin Kramer for reviewing the fix itself. llvm-svn: 160228
* Revert r160194, which switched to use LV information for finding localChandler Carruth2012-07-131-19/+54
| | | | | | | | kills. This is causing miscompiles that I'm working on tracking down. llvm-svn: 160196
* Use the LiveVariables information to efficiently get local kills. ThisChandler Carruth2012-07-131-54/+19
| | | | | | | | | | removes the largest scaling problem in the test cases from PR13225 when ASan is switched to insert basic blocks in the natural CFG order. It may also solve some scaling problems for more normal code with large numbers of basic blocks and variables. llvm-svn: 160194
* Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtualManman Ren2012-07-021-5/+6
| | | | | | | register does not have multiple definitions. Modified TwoAddressInstructionPass to use getUniqueVRegDef instead of getVRegDef. llvm-svn: 159545
* Handle <undef> operands in TwoAddressInstructionPass.Jakob Stoklund Olesen2012-06-251-12/+31
| | | | | | | | | | | | | | | | | When the source register to a 2-addr instruction is undefined, there is no need to attempt any transformations - simply replace the source register with the destination register. This also comes up when lowering IMPLICIT_DEF instructions - make sure the <undef> flag is moved to the new partial register def operand: %vreg8<def> = INSERT_SUBREG %vreg9<undef>, %vreg0<kill>, sub_16bit rewrite undef: %vreg8<def> = INSERT_SUBREG %vreg8<undef>, %vreg0<kill>, sub_16bit convert to: %vreg8:sub_16bit<def,read-undef> = COPY %vreg0<kill> llvm-svn: 159120
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-1/+1
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
* Properly constrain register classes in 2-addr.Jakob Stoklund Olesen2012-05-201-0/+6
| | | | | | | X86 has 2-addr instructions with different constraints on the tied def and use operands. One is GR32, one is GR32_NOSP. llvm-svn: 157149
* Teach two-address pass to update the "source" map so it doesn't perform aEvan Cheng2012-05-181-1/+7
| | | | | | | | | non-profitable commute using outdated info. The test case would still fail because of poor pre-RA schedule. That will be fixed by MI scheduler. rdar://11472010 llvm-svn: 157038
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+1
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng2012-05-031-15/+16
| | | | | | | | | | | | | | | | | | | | | | to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 llvm-svn: 156048
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-031-1/+2
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. llvm-svn: 156046
* Patch r153892 for PR11861 apparently broke an external project (see PR12493).Lang Hames2012-04-091-16/+17
| | | | | | | | | | This patch restores TwoAddressInstructionPass's pre-r153892 behaviour when rescheduling instructions in TryInstructionTransform. Hopefully this will fix PR12493. To refix PR11861, lowering of INSERT_SUBREGS is deferred until after the copy that unties the operands is emitted (this seems to be a more appropriate fix for that issue anyway). llvm-svn: 154338
* REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub ↵Pete Cooper2012-04-041-1/+2
| | | | | | register indices on the source registers. No simple test case llvm-svn: 154051
* Remove spurious debug output.Jakob Stoklund Olesen2012-04-041-1/+0
| | | | llvm-svn: 154032
* During two-address lowering, rescheduling an instruction does not untieLang Hames2012-04-021-2/+2
| | | | | | | operands. Make TryInstructionTransform return false to reflect this. Fixes PR11861. llvm-svn: 153892
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-101-1/+0
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* whitespaceAndrew Trick2012-02-031-8/+8
| | | | llvm-svn: 149671
* Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen2012-01-241-0/+46
| | | | | | | | | | | | | | | | | | | | A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. llvm-svn: 148879
* Preserve <def,undef> flags in CoalesceExtSubRegs.Jakob Stoklund Olesen2012-01-241-3/+7
| | | | | | | This won't have an effect until EliminateRegSequences() starts setting the undef flags. llvm-svn: 148779
* Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper2012-01-181-9/+12
| | | | | | TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE llvm-svn: 148377
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-18/+13
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Simplify code. No functionality change.Benjamin Kramer2011-12-031-2/+1
| | | | | | -3% on ARMDissasembler.cpp. llvm-svn: 145773
* Disable expensive two-address optimizations at -O0. rdar://10453055Evan Cheng2011-11-161-0/+8
| | | | llvm-svn: 144806
* Disable the assertion again. Looks like fastisel is still generating bad ↵Evan Cheng2011-11-161-1/+2
| | | | | | kill markers. llvm-svn: 144804
* Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.Evan Cheng2011-11-161-2/+1
| | | | llvm-svn: 144776
* If the 2addr instruction has other kills, don't move it below any other uses ↵Evan Cheng2011-11-161-2/+7
| | | | | | since we don't want to extend other live ranges. llvm-svn: 144772
* RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE ↵Evan Cheng2011-11-161-1/+1
| | | | | | instructions. rdar://10451185 llvm-svn: 144771
* Process all uses first before defs to accurately capture register liveness. ↵Evan Cheng2011-11-161-7/+13
| | | | | | rdar://10449480 llvm-svn: 144770
* Set SeenStore to true to prevent loads from being moved; also eliminates a ↵Evan Cheng2011-11-151-2/+2
| | | | | | non-deterministic behavior. llvm-svn: 144628
* Avoid dereferencing off the beginning of lists.Evan Cheng2011-11-141-7/+4
| | | | llvm-svn: 144569
* At -O0, multiple uses of a virtual registers in the same BB are being markedEvan Cheng2011-11-141-1/+2
| | | | | | | | "kill". This looks like a bug upstream. Since that's going to take some time to understand, loosen the assertion and disable the optimization when multiple kills are seen. llvm-svn: 144568
* Teach two-address pass to re-schedule two-address instructions (or the killEvan Cheng2011-11-141-19/+356
| | | | | | | | | instructions of the two-address operands) in order to avoid inserting copies. This fixes the few regressions introduced when the two-address hack was disabled (without regressing the improvements). rdar://10422688 llvm-svn: 144559
* PR10998: It is not legal to sink an instruction past the terminator of a ↵Eli Friedman2011-09-231-1/+9
| | | | | | block; make sure we don't do that. llvm-svn: 140428
* Add an isSSA() flag to MachineRegisterInfo.Jakob Stoklund Olesen2011-07-291-0/+3
| | | | | | | | | | | | | This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. llvm-svn: 136532
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-16/+17
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-1/+1
| | | | llvm-svn: 133944
* Simplify code. No change in functionality.Benjamin Kramer2011-06-181-6/+1
| | | | llvm-svn: 133350
* Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich2011-06-071-9/+16
| | | | | | operands to an early clobber register. This fixes <rdar://problem/9566076>. llvm-svn: 132738
* Catch more cases where 2-address pass should 3-addressify instructions. ↵Evan Cheng2011-03-021-49/+70
| | | | | | rdar://9002648. llvm-svn: 126811
* After 3-addressifying a two-address instruction, update the register maps; ↵Evan Cheng2011-02-101-4/+9
| | | | | | add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
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