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path: root/llvm/lib/CodeGen/TargetLoweringBase.cpp
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* Remove trailing spaceFangrui Song2018-07-301-3/+3
* DAG: Add calling convention argument to calling convention funcsMatt Arsenault2018-07-281-3/+4
* Put "built-in" function definitions in global Used list, for LTO. (fix bug 34...Peter Collingbourne2018-07-241-1/+1
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-0/+6
* [AArch64] Gangup loads and stores for pairing.Sirish Pande2018-05-161-0/+1
* [TargetLowering] Use StringRef::split instead of SplitString. NFCCraig Topper2018-05-071-2/+2
* [AArch64] Don't crash trying to resolve __stack_chk_guard.Eli Friedman2018-04-211-2/+5
* [XRay] Typed event logging intrinsicKeith Wyss2018-04-171-0/+15
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to Code...Craig Topper2018-03-291-1/+1
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
* [SelectionDAG] Add LegalTypes flag to getShiftAmountTy. Use it to unify and s...Craig Topper2018-02-201-3/+4
* [XRay][compiler-rt+llvm] Update XRay register stashing semanticsDean Michael Berris2018-02-011-0/+15
* Add support for emitting libcalls for x86_fp80 -> fp128 and vice-versaBenjamin Kramer2018-01-171-0/+6
* TargetLoweringBase: The ios simulator has no bzero function.Matthias Braun2018-01-101-3/+12
* TargetLoweringBase: Fix darwinHasSinCos()Matthias Braun2017-12-191-1/+4
* TargetLoweringBase: Followup to r321035Matthias Braun2017-12-191-2/+3
* TargetLowering: Fix InitLibcallCallingConvs() overriding things set in InitLi...Matthias Braun2017-12-191-7/+3
* TargetLoweringBase: Remove unnecessary watchos exception; NFCMatthias Braun2017-12-181-3/+4
* X86/AArch64/ARM: Factor out common sincos_stret logic; NFCIMatthias Braun2017-12-181-16/+37
* AArch64/X86: Factor out common bzero logic; NFCMatthias Braun2017-12-181-0/+4
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-2/+2
* Relax unaligned access assertion when type is byte alignedDylan McKay2017-12-091-0/+1
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-4/+4
* CodeGen: Minor cleanups to use MachineInstr::getMF. NFCJustin Bogner2017-10-101-1/+1
* [CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What Yo...Eugene Zelenko2017-09-211-19/+38
* [CodeGen][X86] Fuchsia supports sincos* libcalls and sin+cos->sincos optimiza...Petr Hosek2017-07-231-1/+1
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-211-1/+1
* Move Runtime libcall definitions to a .def fileDerek Schuff2017-07-191-438/+8
* Add element atomic memset intrinsicDaniel Neilson2017-07-121-0/+27
* Add element atomic memmove intrinsicDaniel Neilson2017-07-121-0/+27
* [Atomics] Rename and change prototype for atomic memcpy intrinsicDaniel Neilson2017-06-161-12/+16
* Reland "[SelectionDAG] Enable target specific vector scalarization of calls a...Simon Dardis2017-06-091-2/+4
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-031-0/+2
* Do not legalize large setcc with setcce, introduce setcccarry and do it with ...Amaury Sechet2017-06-011-0/+1
* [PPC] Inline expansion of memcmpZaara Syeda2017-05-311-3/+4
* [SelectionDAG] Set ISD::FPOWI to Expand by defaultCraig Topper2017-05-301-0/+1
* BitVector: add iterators for set bitsFrancis Visoiu Mistrih2017-05-171-1/+1
* Do not legalize large add with addc/adde, introduce addcarry and do it with u...Amaury Sechet2017-04-301-0/+4
* TargetLowering: Add finalizeLowering() function; NFCMatthias Braun2017-04-281-0/+5
* [InlineCost] Improve the cost heuristic for SwitchJun Bum Lim2017-04-281-0/+16
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-5/+4
* Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek2017-04-241-4/+5
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-5/+4
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-1/+1
* Module::getOrInsertFunction is using C-style vararg instead of variadic templ...Serge Guelton2017-04-111-1/+1
* Revert "Turn some C-style vararg into variadic templates"Diana Picus2017-04-111-1/+1
* Turn some C-style vararg into variadic templatesSerge Guelton2017-04-111-1/+1
* Revert "[SelectionDAG] Enable target specific vector scalarization of calls a...Simon Dardis2017-04-071-4/+2
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