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* Use MachineInstrBuilder for PHI nodes in SelectionDAGISel.Jakob Stoklund Olesen2012-12-201-50/+25
| | | | llvm-svn: 170716
* Use MachineInstrBuilder in InstrEmitter.Jakob Stoklund Olesen2012-12-202-79/+73
| | | | | | | | | | | | This is supposed to be a mechanical change with no functional effects. InstrEmitter can generate all types of MachineOperands which revealed that MachineInstrBuilder was missing a few methods, added by this patch. Besides providing a context pointer to MI::addOperand(), MachineInstrBuilder seems like a better fit for this code. llvm-svn: 170712
* Do not introduce vector operations in functions marked with noimplicitfloat.Bob Wilson2012-12-201-2/+5
| | | | | | <rdar://problem/12879313> llvm-svn: 170630
* Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT.Patrik Hagglund2012-12-192-8/+9
| | | | | | Accordingly, add MVT::getVT. llvm-svn: 170550
* Split the usage of 'EVT PartVT' into 'MVT PartVT' and 'EVT PartEVT'.Patrik Hagglund2012-12-191-38/+38
| | | | llvm-svn: 170540
* Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,Patrik Hagglund2012-12-192-14/+13
| | | | | | instead of EVTs. llvm-svn: 170538
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-191-1/+1
| | | | | | MVTs, instead of EVTs. llvm-svn: 170537
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-192-14/+19
| | | | | | from EVT. llvm-svn: 170536
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-195-18/+18
| | | | | | EVTs. llvm-svn: 170535
* Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund2012-12-191-4/+4
| | | | | | EVTs. llvm-svn: 170534
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-191-2/+2
| | | | | | of EVT. llvm-svn: 170532
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-192-9/+9
| | | | | | instead of EVTs. llvm-svn: 170529
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-192-12/+15
| | | | llvm-svn: 170524
* Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund2012-12-192-4/+4
| | | | | | EVT. llvm-svn: 170522
* Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund2012-12-192-3/+4
| | | | llvm-svn: 170510
* Optimized load + SIGN_EXTEND patterns in the X86 backend.Elena Demikhovsky2012-12-191-0/+1
| | | | llvm-svn: 170506
* After reducing the size of an operation in the DAG we zero-extend the reducedNadav Rotem2012-12-191-2/+5
| | | | | | | | bitwidth op back to the original size. If we reduce ANDs then this can cause an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits are equal or smaller than the size of the reduced operation. llvm-svn: 170505
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-193-27/+27
| | | | | | single attribute in the future. llvm-svn: 170502
* Remove more of 'else's after 'returns'. No functional change.Craig Topper2012-12-191-6/+6
| | | | llvm-svn: 170497
* Remove a bunch of 'else's after 'returns'Craig Topper2012-12-191-18/+18
| | | | llvm-svn: 170496
* Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be ↵Craig Topper2012-12-191-3/+9
| | | | | | rewritten as a compare against a constant 0 with the opposite condition. llvm-svn: 170495
* Check multiple register classes for inline asm tied registersHal Finkel2012-12-181-3/+16
| | | | | | | | | | | | | | | | | | A register can be associated with several distinct register classes. For example, on PPC, the floating point registers are each associated with both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code would fail when provided with a floating point register and an f64 operand because it would happen to find the register in the F4RC class first and return that. From the F4RC class, SDAG would extract f32 as the register type and then assert because of the invalid implied conversion between the f64 value and the f32 register. Instead, search all register classes. If a register class containing the the requested register has the requested type, then return that register class. Otherwise, as before, return the first register class found that contains the requested register. llvm-svn: 170436
* Revert/correct some FastISel changes in r170104 (EVT->MVT forPatrik Hagglund2012-12-171-5/+6
| | | | | | | | | TargetLowering::getRegClassFor). Some isSimple() guards were missing, or getSimpleVT() were hoisted too far, resulting in asserts on valid LLVM assembly input. llvm-svn: 170336
* Change TargetLowering::getLoadExtAction to take an MVT, instead ofPatrik Hagglund2012-12-141-1/+1
| | | | | | EVT. llvm-svn: 170183
* Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund2012-12-131-1/+1
| | | | llvm-svn: 170148
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-133-11/+11
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 170140
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-136-30/+30
| | | | | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. This is the second attempt. In the first attempt (r169837), a few getSimpleVT() were hoisted too far, detected by bootstrap failures. llvm-svn: 170104
* Fix a bug in DAGCombiner::MatchBSwapHWord. Make sure the node has operands ↵Evan Cheng2012-12-131-1/+2
| | | | | | before referencing them. rdar://12868039 llvm-svn: 170078
* Fix a logic bug in inline expansion of memcpy / memset with an overlappingEvan Cheng2012-12-121-4/+5
| | | | | | | load / store pair. It's not legal to use a wider load than the size of the remaining bytes if it's the first pair of load / store. llvm-svn: 170018
* Sorry about the churn. One more change to getOptimalMemOpType() hook. Did IEvan Cheng2012-12-121-6/+7
| | | | | | | | | | | | mention the inline memcpy / memset expansion code is a mess? This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset. The first indicates whether it is expanding a memset or a memcpy / memmove. The later is whether the memset is a memset of zero. It's totally possible (likely even) that targets may want to do different things for memcpy and memset of zero. llvm-svn: 169959
* - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.Evan Cheng2012-12-121-5/+5
| | | | | | | | | Also added more comments to explain why it is generally ok to return true. - Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to be true for loaded source (memcpy) or zero constants (memset). The poor name choice is probably some kind of legacy issue. llvm-svn: 169954
* DAGCombine: clamp hi bit in APInt::getBitsSet to avoid assertionManman Ren2012-12-121-1/+2
| | | | | | rdar://12838504 llvm-svn: 169951
* Avoid using lossy load / stores for memcpy / memset expansion. e.g.Evan Cheng2012-12-121-15/+21
| | | | | | f64 load / store on non-SSE2 x86 targets. llvm-svn: 169944
* Replace TargetLowering::isIntImmLegal() withEvan Cheng2012-12-111-1/+5
| | | | | | | | | ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined term for something like integer immediate materialization. It is always possible to materialize an integer immediate. Whether to use it for memcpy expansion is more a "cost" conceern. llvm-svn: 169929
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-1115-125/+115
| | | | llvm-svn: 169854
* Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,Patrik Hagglund2012-12-112-13/+12
| | | | | | instead of EVTs. llvm-svn: 169851
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-111-1/+2
| | | | | | | | MVTs, instead of EVTs. Accordingly, add bitsLT (and similar) to MVT. llvm-svn: 169850
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-112-14/+19
| | | | | | from EVT. llvm-svn: 169849
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-115-18/+18
| | | | | | EVTs. llvm-svn: 169848
* Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund2012-12-111-4/+4
| | | | | | EVTs. llvm-svn: 169847
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-111-2/+2
| | | | | | of EVT. llvm-svn: 169845
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-112-8/+8
| | | | | | instead of EVTs. llvm-svn: 169844
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-112-12/+15
| | | | llvm-svn: 169843
* Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund2012-12-112-4/+4
| | | | | | EVT. llvm-svn: 169842
* Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund2012-12-112-3/+4
| | | | llvm-svn: 169841
* Change TargetLowering::getLoadExtAction to take an MVT, instead of EVT.Patrik Hagglund2012-12-111-1/+1
| | | | llvm-svn: 169840
* Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund2012-12-111-1/+1
| | | | llvm-svn: 169839
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-113-11/+11
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 169838
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-116-27/+28
| | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. llvm-svn: 169837
* Fix a miscompile in the DAG combiner. Previously, we would incorrectlyChandler Carruth2012-12-111-2/+6
| | | | | | | | | | | | | | | | | | | | | | | try to reduce the width of this load, and would end up transforming: (truncate (lshr (sextload i48 <ptr> as i64), 32) to i32) to (truncate (zextload i32 <ptr+4> as i64) to i32) We lost the sext attached to the load while building the narrower i32 load, and replaced it with a zext because lshr always zext's the results. Instead, bail out of this combine when there is a conflict between a sextload and a zext narrowing. The rest of the DAG combiner still optimize the code down to the proper single instruction: movswl 6(...),%eax Which is exactly what we wanted. Previously we read past the end *and* missed the sign extension: movl 6(...), %eax llvm-svn: 169802
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