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* Release build: guard dump functions withManman Ren2012-09-112-4/+4
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* Teach DAG combiner to constant fold FABS of a BUILD_VECTOR of ConstantFPs. ↵Craig Topper2012-09-111-22/+47
| | | | | | Factor similar code out of FNEG DAG combiner. llvm-svn: 163587
* Fold multiply by 0 or 1 when in UnsafeFPMath mode in SelectionDAG::getNode().Michael Ilseman2012-09-101-0/+18
| | | | | | This folding happens as early as possible for performance reasons, and to make sure it isn't foiled by other transforms (e.g. forming FMAs). llvm-svn: 163519
* whitespaceMichael Ilseman2012-09-101-10/+10
| | | | llvm-svn: 163518
* Fix an assertion failure when optimising a shufflevector incorrectly into ↵James Molloy2012-09-102-10/+12
| | | | | | concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types. llvm-svn: 163511
* Teach the DAGBuilder about lifetime markers which are generated from PHINodes.Nadav Rotem2012-09-101-18/+22
| | | | llvm-svn: 163494
* Teach DAG combiner to constant fold fneg of a BUILD_VECTOR of constants.Craig Topper2012-09-091-1/+25
| | | | llvm-svn: 163483
* Stop emitting lifetime region info when stack coloring is not enabled in O0Michael Liao2012-09-071-0/+6
| | | | | | - this should fix PR13780 llvm-svn: 163370
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-062-0/+8
| | | | | | No functional change. llvm-svn: 163339
* Fix a few old-GCC warnings. No functional change.Nadav Rotem2012-09-061-1/+1
| | | | llvm-svn: 163309
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-067-7/+46
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* Cleanup a few magic numbers.Chad Rosier2012-09-051-1/+1
| | | | llvm-svn: 163263
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-052-3/+3
| | | | llvm-svn: 163258
* [ms-inline asm] We only need one bit to represent the AsmDialect in theChad Rosier2012-09-051-4/+2
| | | | | | MachineInstr. llvm-svn: 163257
* Constify this properly. Found by gcc48 -Wcast-qual.Roman Divacky2012-09-051-4/+4
| | | | llvm-svn: 163256
* Constify SDNodeIterator an stop its only non-const user being cast strippedRoman Divacky2012-09-051-1/+1
| | | | | | of its constness. Found by gcc48 -Wcast-qual. llvm-svn: 163254
* [ms-inline asm] Propagate the asm dialect into the MachineInstr representation.Chad Rosier2012-09-051-1/+5
| | | | llvm-svn: 163243
* Fixed the DAG combiner to better handle the folding of AND nodes for vector ↵Silviu Baranga2012-09-051-1/+11
| | | | | | types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value. llvm-svn: 163203
* Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG ↵Craig Topper2012-09-051-1/+15
| | | | | | build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. llvm-svn: 163192
* Generic Bypass Slow DivPreston Gurd2012-09-041-1/+0
| | | | | | | | | | | | | | | | | | | | | | | - CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! llvm-svn: 163150
* Fix a typo.Nadav Rotem2012-09-021-1/+1
| | | | llvm-svn: 163094
* Generate better select code by allowing the target to use scalar select, and ↵Nadav Rotem2012-09-021-4/+3
| | | | | | not sign-extend. llvm-svn: 163086
* Only legalise a VSELECT in to bitwise operations if the vector mask bool is ↵Pete Cooper2012-09-011-1/+6
| | | | | | | | | zeros or all ones. A vector bool with just ones isn't suitable for masking with. No test case unfortunately as i couldn't find a target which fit all the conditions needed to hit this code. llvm-svn: 163075
* Revert "Take account of boolean vector contents when promoting a build ↵Pete Cooper2012-09-011-17/+1
| | | | | | | | | | | | | | vector from i1 to some other type. rdar://problem/12210060" This reverts commit 5dd9e214fb92847e947f9edab170f9b4e52b908f. Thanks to Duncan for explaining how this should have been done. Conflicts: test/CodeGen/X86/vec_select.ll llvm-svn: 163064
* Teach DAG combine a number of tricks to simplify FMA expressions in ↵Owen Anderson2012-09-011-0/+64
| | | | | | fast-math mode. llvm-svn: 163051
* Fix typoMichael Liao2012-09-011-1/+1
| | | | llvm-svn: 163049
* Add MachineInstr::tieOperands, remove setIsTied().Jakob Stoklund Olesen2012-08-311-6/+2
| | | | | | | | | | | Manage tied operands entirely internally to MachineInstr. This makes it possible to change the representation of tied operands, as I will do shortly. The constraint that tied uses and defs must be in the same order was too restrictive. llvm-svn: 163021
* Don't enforce ordered inline asm operands.Jakob Stoklund Olesen2012-08-311-10/+0
| | | | | | | | | I was too optimistic, inline asm can have tied operands that don't follow the def order. Fixes PR13742. llvm-svn: 162998
* Take account of boolean vector contents when promoting a build vector from ↵Pete Cooper2012-08-301-1/+17
| | | | | | i1 to some other type. rdar://problem/12210060 llvm-svn: 162960
* Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by ↵Owen Anderson2012-08-301-1/+122
| | | | | | constants. This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants. llvm-svn: 162956
* Currently targets that do not support selects with scalar conditions and ↵Nadav Rotem2012-08-301-1/+65
| | | | | | | | | | | vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926
* Add FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be ↵Craig Topper2012-08-301-0/+1
| | | | | | expanded when it isn't legal. llvm-svn: 162894
* Add support for FMA to WidenVectorResult.Craig Topper2012-08-302-0/+14
| | | | llvm-svn: 162893
* Verify the order of tied operands in inline asm.Jakob Stoklund Olesen2012-08-291-0/+12
| | | | | | | | | | | | | | When there are multiple tied use-def pairs on an inline asm instruction, the tied uses must appear in the same order as the defs. It is possible to write an LLVM IR inline asm instruction that breaks this constraint, but there is no reason for a front end to emit the operands out of order. The gnu inline asm syntax specifies tied operands as a single read/write constraint "+r", so ouf of order operands are not possible. llvm-svn: 162878
* Set the isTied flags when building INLINEASM MachineInstrs.Jakob Stoklund Olesen2012-08-291-4/+21
| | | | | | | | For normal instructions, isTied() is set automatically by addOperand(), based on MCInstrDesc, but inline asm has tied operands outside the descriptor. llvm-svn: 162869
* Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen2012-08-281-18/+23
| | | | | | | | | | | | | | | These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. llvm-svn: 162733
* Fix bug 13532.Akira Hatanaka2012-08-281-1/+1
| | | | | | | | | In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without using any f64 operations if f64 is not a legal type. Patch by Stefan Kristiansson. llvm-svn: 162728
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-3/+2
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Avoid including explicit uses when counting SDNode imp-uses.Jakob Stoklund Olesen2012-08-241-3/+6
| | | | | | | It is legal to have a register node as an explicit operand, it shouldn't be counted as an implicit use. llvm-svn: 162591
* BranchProb: modify the definition of an edge in BranchProbabilityInfo to handleManman Ren2012-08-243-28/+60
| | | | | | | | | | | | | | the case of multiple edges from one block to another. A simple example is a switch statement with multiple values to the same destination. The definition of an edge is modified from a pair of blocks to a pair of PredBlock and an index into the successors. Also set the weight correctly when building SelectionDAG from LLVM IR, especially when converting a Switch. IntegersSubsetMapping is updated to calculate the weight for each cluster. llvm-svn: 162572
* Rejected 169195. As Duncan commented, bitcasting to proper type is wrong ↵Stepan Dyatkovskiy2012-08-221-23/+3
| | | | | | approach. We need to insert some valid TRANCATE node here. llvm-svn: 162354
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-222-5/+4
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Initialize SelectionDAGBuilder's Context in 'init', not in its constructor. TheRichard Smith2012-08-222-1/+2
| | | | | | | | SelectionDAG's 'init' has not been called when the SelectionDAGBuilder is constructed (in SelectionDAGISel's constructor), so this was previously always initialized with 0. llvm-svn: 162333
* Don't add CFG edges for redundant conditional branches.Jakob Stoklund Olesen2012-08-201-1/+4
| | | | | | | | | | | | | IR that hasn't been through SimplifyCFG can look like this: br i1 %b, label %r, label %r Make sure we don't create duplicate Machine CFG edges in this case. Fix the machine code verifier to accept conditional branches with a single CFG edge. llvm-svn: 162230
* Fixed DAGCombiner bug (found and localized by James Malloy):Stepan Dyatkovskiy2012-08-201-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DAGCombiner tries to optimise a BUILD_VECTOR by checking if it consists purely of get_vector_elts from one or two source vectors. If so, it either makes a concat_vectors node or a shufflevector node. However, it doesn't check the element type width of the underlying vector, so if you have this sequence: Node0: v4i16 = ... Node1: i32 = extract_vector_elt Node0 Node2: i32 = extract_vector_elt Node0 Node3: v16i8 = BUILD_VECTOR Node1, Node2, ... It will attempt to: Node0: v4i16 = ... NewNode1: v16i8 = concat_vectors Node0, ... Where this is actually invalid because the element width is completely different. This causes an assertion failure on DAG legalization stage. Fix: If output item type of BUILD_VECTOR differs from input item type. Make concat_vectors based on input element type and then bitcast it to the output vector type. So the case described above will transformed to: Node0: v4i16 = ... NewNode1: v8i16 = concat_vectors Node0, ... NewNode2: v16i8 = bitcast NewNode1 llvm-svn: 162195
* Make atomic load and store of pointers work. Tighten verification of atomic ↵Eli Friedman2012-08-171-2/+2
| | | | | | | | | operations so other unexpected operations don't slip through. Based on patch by Logan Chien. PR11786/PR13186. llvm-svn: 162146
* TargetLowering: Use the large shift amount during legalize types. The ↵Benjamin Kramer2012-08-171-3/+3
| | | | | | legalizer may call us with an overly large type. llvm-svn: 162101
* Add a roundToIntegral method to APFloat, which can be parameterized over ↵Owen Anderson2012-08-132-0/+60
| | | | | | various rounding modes. Use this to implement SelectionDAG constant folding of FFLOOR, FCEIL, and FTRUNC. llvm-svn: 161807
* Fix the legalization of ExtLoad on ARM. ExpandUnalignedLoad did not properly Nadav Rotem2012-08-091-3/+4
| | | | | | | handle the cases where the memory value type was illegal. PR 13111. llvm-svn: 161565
* Add SelectionDAG::getTargetIndex.Jakob Stoklund Olesen2012-08-074-0/+35
| | | | | | | This adds support for TargetIndex operands during isel. The meaning of these (index, offset, flags) operands is entirely defined by the target. llvm-svn: 161453
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