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* Avoid generating ISD::SELECT for vector operands to SIGN_EXTENDRichard Relph2013-03-121-2/+2
| | | | llvm-svn: 176881
* Fix a crasher newly introduced in r176659/r176649, where fast-isel tries toNick Lewycky2013-03-111-0/+2
| | | | | | lower an expect intrinsic that is a constant expression. llvm-svn: 176830
* Disable statistics on Release builds and move tests that depend on -stats.Jan Wen Voung2013-03-082-18/+14
| | | | | | | | | | | | | | | | | Summary: Statistics are still available in Release+Asserts (any +Asserts builds), and stats can also be turned on with LLVM_ENABLE_STATS. Move some of the FastISel stats that were moved under DEBUG() back out of DEBUG(), since stats are disabled across the board now. Many tests depend on grepping "-stats" output. Move those into a orig_dir/Stats/. so that they can be marked as unsupported when building without statistics. Differential Revision: http://llvm-reviews.chandlerc.com/D486 llvm-svn: 176733
* Remove default from fully covered switch.Benjamin Kramer2013-03-081-2/+1
| | | | llvm-svn: 176703
* LegalizeDAG: Respect the result of TLI.getBooleanContents() when expanding SETCCTom Stellard2013-03-081-1/+13
| | | | llvm-svn: 176695
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-081-1/+2
| | | | | | | | | | | | | LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. llvm-svn: 176694
* Revert r176154 in favor of a better approach.Bill Wendling2013-03-081-7/+0
| | | | | | | | | | | | | | | | | | | Code generation makes some basic assumptions about the IR it's been given. In particular, if there is only one 'invoke' in the function, then that invoke won't be going away. However, with the advent of the `llvm.donothing' intrinsic, those invokes may go away. If all of them go away, the landing pad no longer has any users. This confuses the back-end, which asserts. This happens with SjLj exceptions, because that's the model that modifies the IR based on there being invokes, etc. in the function. Remove any invokes of `llvm.donothing' during SjLj EH preparation. This will give us a CFG that the back-end won't be confused about. If all of the invokes in a function are removed, then the SjLj EH prepare pass won't insert the bogus code the relies upon the invokes being there. <rdar://problem/13228754&13316637> llvm-svn: 176677
* [fast-isel] Seriously, add support for the expect intrinsic.Chad Rosier2013-03-071-3/+3
| | | | | | rdar://13370942 llvm-svn: 176659
* [fast-isel] Add support for the expect intrinsic.Chad Rosier2013-03-071-0/+5
| | | | | | rdar://13370942 llvm-svn: 176649
* ArrayRefize some code. No functionality change.Benjamin Kramer2013-03-072-5/+3
| | | | llvm-svn: 176648
* pre-RA-sched debug-only fixAndrew Trick2013-03-071-2/+4
| | | | llvm-svn: 176638
* pre-RA-sched assertion fix. This bug was exposed by r176037.Andrew Trick2013-03-071-3/+0
| | | | | | | | | | | | | rdar:13370002 [pre-RA-sched] assertion: released too many times I tracked this down to an earlier hack that is no longer applicable and interfered with normal scheduler logic. With the changes in r176037, it was causing an instruction to be scheduled multiple times. I have an external test case that I tried hard to reduce and failed. I can't even reproduce with llc. llvm-svn: 176636
* No need to go through int64 and APInt when generating a new constant.Nadav Rotem2013-03-071-3/+3
| | | | llvm-svn: 176615
* SDAG: Handle scalarizing an extend of a <1 x iN> vector.Jim Grosbach2013-03-072-0/+21
| | | | | | | | | Just scalarize the element and rebuild a vector of the result type from that. rdar://13281568 llvm-svn: 176614
* Remove duplicate line and move another closer to its actual useEli Bendersky2013-03-011-3/+1
| | | | llvm-svn: 176391
* Set properties for f128 type.Akira Hatanaka2013-03-011-17/+62
| | | | llvm-svn: 176378
* Generate an error message instead of asserting or segfaulting when we can'tChad Rosier2013-03-011-0/+1
| | | | | | | handle indirect register inputs. rdar://13322011 llvm-svn: 176367
* Fix PR10475Michael Liao2013-03-013-12/+17
| | | | | | | | | | | | | | - ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. llvm-svn: 176364
* A small refactoring + adding comments.Eli Bendersky2013-02-282-10/+5
| | | | | | | | | | | SelectionDAGIsel::LowerArguments needs a function, not a basic block. So it makes sense to pass it the function instead of extracting a basic-block from the function and then tossing it. This is also more self-documenting (functions have arguments, BBs don't). In addition, added comments to a couple of Select* methods. llvm-svn: 176305
* Put some per-instruction statistics of fast isel under NDEBUG, together withEli Bendersky2013-02-281-3/+5
| | | | | | other per-instruction statistics. llvm-svn: 176273
* Remove unnecessary cast to void.Eric Christopher2013-02-271-1/+0
| | | | llvm-svn: 176222
* Silence the unused variable warning. Nadav Rotem2013-02-271-5/+7
| | | | llvm-svn: 176218
* The FastISEL should be fast. But when we record statistics we use atomic ↵Nadav Rotem2013-02-271-9/+10
| | | | | | | | operations to increment the counters. This patch disables the counters on non-debug builds. This reduces the runtime of SelectionDAGISel::SelectCodeCommon by ~5%. llvm-svn: 176214
* Reverted: r176136 - Have a way for a target to opt-out of target-independent ↵Michael Ilseman2013-02-271-1/+1
| | | | | | fast isel llvm-svn: 176204
* SelectionDAG: If llvm.donothing has a landingpad, we should clearManman Ren2013-02-271-0/+7
| | | | | | | | | CurrentCallSite to avoid an assertion failure: assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); rdar://problem/13228754 llvm-svn: 176154
* Have a way for a target to opt-out of target-independent fast iselMichael Ilseman2013-02-261-1/+1
| | | | llvm-svn: 176136
* Fix wording.Chad Rosier2013-02-251-3/+4
| | | | llvm-svn: 176055
* [fast-isel] Add X86FastIsel::FastLowerArguments to handle functions with 6 orChad Rosier2013-02-251-0/+10
| | | | | | | | | | fewer scalar integer (i32 or i64) arguments. It completely eliminates the need for SDISel for trivial functions. Also, add the new llc -fast-isel-abort-args option, which is similar to -fast-isel-abort option, but for formal argument lowering. llvm-svn: 176052
* pre-RA-sched fix: only reevaluate physreg interferences when necessary.Andrew Trick2013-02-251-33/+61
| | | | | | Fixes rdar:13279013: scheduler was blowing up on select instructions. llvm-svn: 176037
* 'Hexadecimal' has two 'a's and only one 'i'.Matt Beaumont-Gay2013-02-251-2/+2
| | | | llvm-svn: 176031
* Fix spelling noticed by Duncan.Chandler Carruth2013-02-251-3/+3
| | | | llvm-svn: 176023
* Fix the root cause of PR15348 by correctly handling alignment 0 onChandler Carruth2013-02-252-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | memory intrinsics in the SDAG builder. When alignment is zero, the lang ref says that *no* alignment assumptions can be made. This is the exact opposite of the internal API contracts of the DAG where alignment 0 indicates that the alignment can be made to be anything desired. There is another, more explicit alignment that is better suited for the role of "no alignment at all": an alignment of 1. Map the intrinsic alignment to this early so that we don't end up generating aligned DAGs. It is really terrifying that we've never seen this before, but we suddenly started generating a large number of alignment 0 memcpys due to the new code to do memcpy-based copying of POD class members. That patch contains a bug that rounds bitfield alignments down when they are the first field. This can in turn produce zero alignments. This fixes weird crashes I've seen in library users of LLVM on 32-bit hosts, etc. llvm-svn: 176022
* SelectionDAG compile time improvement.Nadav Rotem2013-02-221-0/+19
| | | | | | | | One of the phases of SelectionDAG is LegalizeVectors. We don't need to sort the DAG and copy nodes around if there are no vector ops. Speeds up the compilation time of SelectionDAG on a big scalar workload by ~8%. llvm-svn: 175929
* Fix isa<> check which could never be true.Pete Cooper2013-02-221-1/+1
| | | | | | | | | | | | It was incorrectly checking a Function* being an IntrinsicInst* which isn't possible. It should always have been checking the CallInst* instead. Added test case for x86 which ensures we only get one constant load. It was 2 before this change. rdar://problem/13267920 llvm-svn: 175853
* DAGCombiner: Make the post-legalize vector op optimization more aggressive.Benjamin Kramer2013-02-211-10/+0
| | | | | | | | A legal BUILD_VECTOR goes in and gets constant folded into another legal BUILD_VECTOR so we don't lose any legality here. The problematic PPC optimization that made this check necessary was fixed recently. llvm-svn: 175759
* DAGCombiner: Fold pointless truncate, bitcast, buildvector seriesArnold Schwaighofer2013-02-201-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | (2xi32) (truncate ((2xi64) bitcast (buildvector i32 a, i32 x, i32 b, i32 y))) can be folded into a (2xi32) (buildvector i32 a, i32 b). Such a DAG would cause uneccessary vdup instructions followed by vmovn instructions. We generate this code on ARM NEON for a setcc olt, 2xf64, 2xf64. For example, in the vectorized version of the code below. double A[N]; double B[N]; void test_double_compare_to_double() { int i; for(i=0;i<N;i++) A[i] = (double)(A[i] < B[i]); } radar://13191881 Fixes bug 15283. llvm-svn: 175670
* Fix PR15267Michael Liao2013-02-201-14/+119
| | | | | | | | | - When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. llvm-svn: 175642
* Move the SplatByte helper to APInt and generalize it a bit.Benjamin Kramer2013-02-202-29/+7
| | | | llvm-svn: 175621
* Fix #includes, so we include only what we really need.Jakub Staszak2013-02-201-1/+1
| | | | llvm-svn: 175581
* [ms-inline asm] Remove a redundant call to the setHasMSInlineAsm function.Chad Rosier2013-02-181-2/+1
| | | | llvm-svn: 175456
* [ms-inline asm] Fix undefined behavior to reset hasMSInlineAsm in advance of ↵NAKAMURA Takumi2013-02-181-0/+1
| | | | | | SelectAllBasicBlocks(). llvm-svn: 175422
* LegalizeDAG.cpp doesn't need DenseMap.Jakub Staszak2013-02-161-1/+0
| | | | llvm-svn: 175365
* [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.Chad Rosier2013-02-161-14/+17
| | | | | | | | | | | If the frame pointer is omitted, and any stack changes occur in the inline assembly, e.g.: "pusha", then any C local variable or C argument references will be incorrect. I pass no judgement on anyone who would do such a thing. ;) rdar://13218191 llvm-svn: 175334
* Use the 'target-features' and 'target-cpu' attributes to reset the subtarget ↵Bill Wendling2013-02-151-0/+4
| | | | | | | | | | features. If two functions require different features (e.g., `-mno-sse' vs. `-msse') then we want to honor that, especially during LTO. We can do that by resetting the subtarget's features depending upon the 'target-feature' attribute. llvm-svn: 175314
* enable SDISel sincos optimization for GNU environmentsPaul Redmond2013-02-151-1/+16
| | | | | | | | | | | | - add sincos to runtime library if target triple environment is GNU - added canCombineSinCosLibcall() which checks that sincos is in the RTL and if the environment is GNU then unsafe fpmath is enabled (required to preserve errno) - extended sincos-opt lit test Reviewed by: Hal Finkel llvm-svn: 175283
* Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.Nadav Rotem2013-02-141-6/+6
| | | | llvm-svn: 175190
* Add some legality checks for SETCC before introducing it in the DAG combiner ↵Owen Anderson2013-02-141-2/+6
| | | | | | post-operand legalization. llvm-svn: 175149
* Add static cast to unsigned char whenever a character classification ↵Guy Benyei2013-02-121-1/+1
| | | | | | function is called with a signed char argument, in order to avoid assertions in Windows Debug configuration. llvm-svn: 175006
* PR14562 - Truncation of left shift became undefPaul Redmond2013-02-121-2/+9
| | | | | | | | | | | DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32)) into (shl i32 v, 32) into undef. To prevent this, check the shift count against the final result size. Patch by: Kevin Schoedel Reviewed by: Nadav Rotem llvm-svn: 174972
* Check type for legality before forming a select from loads.Pete Cooper2013-02-121-1/+3
| | | | | | | | Sorry for the lack of a test case. I tried writing one for i386 as i know selects are illegal on this target, but they are actually considered legal by isel and expanded later. I can't see any targets to trigger this, but checking for the legality of a node before forming it is general goodness. llvm-svn: 174934
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