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* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-041-0/+27
| | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. llvm-svn: 191940
* Added checking code whehter target supports specific dag combining about rotateJin-Gu Kang2013-10-031-11/+19
| | | | | | | | | | | | | | | | | | | | | | | or not. The corresponding dag patterns are as following: "DAGCombier::MatchRotate" function in DAGCombiner.cpp Pattern1 // fold (or (shl (*ext x), (*ext y)), // (srl (*ext x), (*ext (sub 32, y)))) -> // (*ext (rotl x, y)) // fold (or (shl (*ext x), (*ext y)), // (srl (*ext x), (*ext (sub 32, y)))) -> // (*ext (rotr x, (sub 32, y))) pattern2 // fold (or (shl (*ext x), (*ext (sub 32, y))), // (srl (*ext x), (*ext y))) -> // (*ext (rotl x, y)) // fold (or (shl (*ext x), (*ext (sub 32, y))), // (srl (*ext x), (*ext y))) -> // (*ext (rotr x, (sub 32, y))) llvm-svn: 191905
* Remove several unused variables.Rafael Espindola2013-10-012-5/+2
| | | | | | Patch by Alp Toker. llvm-svn: 191757
* SelectionDAG: Clarify comments from r191600Tom Stellard2013-10-011-2/+2
| | | | llvm-svn: 191724
* Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.Benjamin Kramer2013-09-291-2/+10
| | | | | | | SDNode destructors are never called. As an optimization use AtomicSDNode's internal storage if we have a small number of operands. llvm-svn: 191636
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-281-1/+1
| | | | llvm-svn: 191610
* SelectionDAG: Silence unused variable warning on release buildsTom Stellard2013-09-281-0/+1
| | | | llvm-svn: 191604
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-281-13/+37
| | | | | | | | | | | SelectionDAG will now attempt to inverse an illegal conditon in order to find a legal one and if that doesn't work, it will attempt to swap the operands using the inverted condition. There are no new test cases for this, but a nubmer of the existing R600 tests hit this path. llvm-svn: 191602
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-283-18/+33
| | | | | | | | | | | | This is useful for targets like R600, which only support GT, GE, NE, and EQ condition codes as it removes the need to handle unsupported condition codes in target specific code. There are no tests with this commit, but R600 has been updated to take advantage of this new feature, so its existing selectcc tests are now testing the swapped operands path. llvm-svn: 191601
* SelectionDAG: Clean up LegalizeSetCCCondCode() functionTom Stellard2013-09-281-26/+51
| | | | | | | | | | | | | | Interpreting the results of this function is not very intuitive, so I cleaned it up to make it more clear whether or not a SETCC op was legalized and how it was legalized (either by swapping LHS and RHS or replacing with AND/OR). This patch does change functionality in the LHS and RHS swapping case, but unfortunately there are no in-tree tests for this. However, this patch is a prerequisite for R600 to take advantage of the LHS and RHS swapping, so tests will be added in subsequent commits. llvm-svn: 191600
* Re-apply the change from r191393 with fix for pr17380.Andrea Di Biagio2013-09-271-0/+20
| | | | | | | | | | This change fixes the problem reported in pr17380 and re-add the dagcombine transformation ensuring that the value types are always legal if the transformation is triggered after Legalization took place. Added the test case from pr17380. llvm-svn: 191509
* Revert r191393 since it caused pr17380.Andrea Di Biagio2013-09-261-20/+0
| | | | llvm-svn: 191438
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-48/+26
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191428
* Added temp flag -misched-bench for staging in default changes.Andrew Trick2013-09-261-1/+1
| | | | llvm-svn: 191423
* whitespaceAndrew Trick2013-09-261-2/+2
| | | | llvm-svn: 191422
* Teach DAGCombiner how to canonicalize dags according to the ruleAndrea Di Biagio2013-09-251-0/+20
| | | | | | | | | | | | (shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)). The rule only triggers when there are no other uses of the zext to avoid materializing more instructions. This helps the DAGCombiner understand that the shl/shr sequence can then be converted into an and instruction. llvm-svn: 191393
* Add missing check to SETCC optimization.Eli Friedman2013-09-241-0/+1
| | | | | | PR17338. llvm-svn: 191337
* DAGCombiner: Unify rotate matching for extended and unextended amounts.Benjamin Kramer2013-09-241-79/+57
| | | | | | No functionality change, lots of indentation changes. llvm-svn: 191303
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-241-1/+2
| | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. llvm-svn: 191263
* [stackprotector] Allow for copies from vreg -> vreg to be in a terminator ↵Michael Gottesman2013-09-241-6/+26
| | | | | | | | | | | sequence. Sometimes a copy from a vreg -> vreg sneaks into the middle of a terminator sequence. It is safe to slice this into the stack protector success bb. This fixes PR16979. llvm-svn: 191260
* fix typo: than -> thenKay Tiong Khoo2013-09-231-1/+1
| | | | llvm-svn: 191214
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-5/+5
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
* Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs ↵Juergen Ributzka2013-09-212-35/+8
| | | | | | | | splitting too." This reverts commit r191130. llvm-svn: 191138
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-09-212-8/+35
| | | | | | | | | | | | | | | | | | The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask for the given target. This mask has usually te same size as the VSELECT return type (except for Intel KNL). Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. llvm-svn: 191130
* Add braces to suppress Clang's dangling-else warning.David Blaikie2013-09-201-2/+4
| | | | | | These violations were introduced in r191049 llvm-svn: 191059
* PR16726: extend rol/ror matchingKai Nacke2013-09-191-2/+37
| | | | | | | | | | | | | | | | | | | | | C-like languages promote types like unsigned short to unsigned int before performing an arithmetic operation. Currently the rotate matcher in the DAGCombiner does not consider this situation. This commit extends the DAGCombiner in the way that the pattern (or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y)))) is folded into ([az]ext (rotl x, y)) The matching is restricted to aext and zext because in this cases the upper bits are either undefined or known. Test case is included. This fixes PR16726. llvm-svn: 191049
* Revert PR16726: extend rol/ror matchingKai Nacke2013-09-191-35/+0
| | | | | | There is a buildbot failure. Need to investigate this. llvm-svn: 191048
* PR16726: extend rol/ror matchingKai Nacke2013-09-191-0/+35
| | | | | | | | | | | | | | | | | | | | | C-like languages promote types like unsigned short to unsigned int before performing an arithmetic operation. Currently the rotate matcher in the DAGCombiner does not consider this situation. This commit extends the DAGCombiner in the way that the pattern (or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y)))) is folded into ([az]ext (rotl x, y)) The matching is restricted to aext and zext because in this cases the upper bits are either undefined or known. Test case is included. This fixes PR16726. llvm-svn: 191045
* DAGCombiner: Don't fold vector muls with constants that look like a splat of ↵Benjamin Kramer2013-09-191-3/+7
| | | | | | | | a power of 2 but differ in bit width. PR17283. llvm-svn: 191000
* Debug info: Get rid of the VLA indirection hack in FastISel.Adrian Prantl2013-09-181-15/+10
| | | | | | | | Use the DIVariable::isIndirect() flag set by the frontend instead of guessing whether to set the machine location's indirection bit. Paired commit with CFE. llvm-svn: 190961
* Added documentation to getMemsetStores.Serge Pavlov2013-09-171-0/+18
| | | | llvm-svn: 190866
* [SelectionDAG] Teach the vector scalarizer about TRUNCATE.Quentin Colombet2013-09-172-3/+4
| | | | | | | | | | | When a truncate node defines a legal vector type but uses an illegal vector type, the legalization process was splitting the vector until <1 x vector> type, but then it was failing to scalarize the node because it did not know how to handle TRUNCATE. <rdar://problem/14989896> llvm-svn: 190830
* Debug info: Fix PR16736 and rdar://problem/14990587.Adrian Prantl2013-09-162-1/+2
| | | | | | | A DBG_VALUE is register-indirect iff the first operand is a register _and_ the second operand is an immediate. llvm-svn: 190821
* Prevent assert in CombinerGlobalAA with null valuesHal Finkel2013-09-151-1/+1
| | | | | | | DAGCombiner::isAlias can be called with SrcValue1 or SrcValue2 null, and we can't use AA in this case (if we try, then the casting code in AA will assert). llvm-svn: 190763
* Remove pointless assertion after r190376Matt Arsenault2013-09-121-2/+0
| | | | llvm-svn: 190565
* Revert "Give internal classes hidden visibility."Benjamin Kramer2013-09-114-4/+4
| | | | | | | It works with clang, but GCC has different rules so we can't make all of those hidden. This reverts commit r190534. llvm-svn: 190536
* Give internal classes hidden visibility.Benjamin Kramer2013-09-114-4/+4
| | | | | | Worth 100k on a linux/x86_64 Release+Asserts clang. llvm-svn: 190534
* Rename variables for consistency.Eli Friedman2013-09-111-6/+6
| | | | | | No functional change. llvm-svn: 190466
* Fix unused variables.Eli Friedman2013-09-101-1/+0
| | | | llvm-svn: 190448
* Don't use getSetCCResultType for creating a vselectMatt Arsenault2013-09-101-2/+1
| | | | | | | | | | | | | | | | | | | The vselect mask isn't a setcc. This breaks in the case when the result of getSetCCResultType is larger than the vector operands e.g. %tmp = select i1 %cmp <2 x i8> %a, <2 x i8> %b when getSetCCResultType returns <2 x i32>, the assertion that the (MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits()) is hit. No test since I don't think I can hit this with any of the current targets. The R600/SI implementation would break, since it returns a vector of i1 for this, but it doesn't reach ExpandSELECT for other reasons. llvm-svn: 190376
* white spaces and long linesJack Carter2013-09-091-45/+81
| | | | llvm-svn: 190358
* Revert patches to add case-range support for PR1255.Bob Wilson2013-09-092-36/+53
| | | | | | | | | | | | | | | | | The work on this project was left in an unfinished and inconsistent state. Hopefully someone will eventually get a chance to implement this feature, but in the meantime, it is better to put things back the way the were. I have left support in the bitcode reader to handle the case-range bitcode format, so that we do not lose bitcode compatibility with the llvm 3.3 release. This reverts the following commits: 155464, 156374, 156377, 156613, 156704, 156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575, 157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884, 157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100, 159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659, 159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736 llvm-svn: 190328
* SelectionDAG: create correct BooleanContent constantsTim Northover2013-09-062-2/+11
| | | | | | | | | | | | | | | Occasionally DAGCombiner can spot that a SETCC operation is completely redundant and reduce it to "all true" or "all false". If this happens to a vector, the value produced has to take account of what a normal comparison would have produced, which may be an all-1s bitmask. The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when triggered so there are no tests. However, I believe it's still clearly the right change and may save someone else some hassle if it suddenly becomes reachable. So I'm doing it anyway. llvm-svn: 190147
* Use TargetSubtargetInfo::useAA() in DAGCombineHal Finkel2013-08-291-3/+10
| | | | | | | This uses the TargetSubtargetInfo::useAA() function to control the defaults of the -combiner-alias-analysis and -combiner-global-alias-analysis options. llvm-svn: 189564
* Fix a typo and coding style of a previous commit. No functional change.Juergen Ributzka2013-08-281-3/+2
| | | | llvm-svn: 189526
* DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswapTim Northover2013-08-271-6/+24
| | | | | | | | We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N), const), but this is only valid if the bits above 16 on the source pattern are 0, the checks we were doing on this were slightly wrong before. llvm-svn: 189348
* Remove an over-zealous assertion. A pointer type could be illegal if the ↵Owen Anderson2013-08-271-1/+0
| | | | | | target is prepared to custom-legalize pointer operands. This assertion was evaluated before the target would have a chance to do so, making it impossible. llvm-svn: 189299
* SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()Tom Stellard2013-08-267-43/+50
| | | | | | | | | | | | If we have a binary operation like ISD:ADD, we can set the result type equal to the result type of one of its operands rather than using TargetLowering::getPointerTy(). Also, any use of DAG.getIntPtrConstant(C) as an operand for a binary operation can be replaced with: DAG.getConstant(C, OtherOperand.getValueType()); llvm-svn: 189227
* SelectionDAG: Use correct pointer size when splitting vector storesTom Stellard2013-08-261-1/+1
| | | | llvm-svn: 189224
* SelectionDAG: Use correct pointer size when lowering function arguments v2Tom Stellard2013-08-261-5/+8
| | | | | | | | | | | | | | | | This adds minimal support to the SelectionDAG for handling address spaces with different pointer sizes. The SelectionDAG should now correctly lower pointer function arguments to the correct size as well as generate the correct code when lowering getelementptr. This patch also updates the R600 DataLayout to use 32-bit pointers for the local address space. v2: - Add more helper functions to TargetLoweringBase - Use CHECK-LABEL for tests llvm-svn: 189221
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