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* whitespaceAndrew Trick2010-12-242-172/+172
| | | | llvm-svn: 122539
* flags -> glue for selectiondagChris Lattner2010-12-236-78/+77
| | | | llvm-svn: 122509
* sdisel flag -> glue.Chris Lattner2010-12-231-77/+76
| | | | llvm-svn: 122507
* Reorganize ListScheduleBottomUp in preparation for modeling machine cycles ↵Andrew Trick2010-12-231-130/+153
| | | | | | and instruction issue. llvm-svn: 122491
* Converted LiveRegCycles to LiveRegGens. It's easier to work with and allows ↵Andrew Trick2010-12-231-17/+18
| | | | | | multiple nodes per cycle. llvm-svn: 122474
* In CheckForLiveRegDef use TRI->getOverlaps.Andrew Trick2010-12-231-6/+9
| | | | llvm-svn: 122473
* Fixes PR8823: add-with-overflow-128.llAndrew Trick2010-12-231-12/+33
| | | | | | | | In the bottom-up selection DAG scheduling, handle two-address instructions that read/write unspillable registers. Treat the entire chain of two-address nodes as a single live range. llvm-svn: 122472
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-231-6/+6
| | | | | | | new gcc warning that complains on self-assignments and self-initializations. llvm-svn: 122458
* DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is ↵Benjamin Kramer2010-12-221-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | illegal. The latter usually compiles into smaller code. example code: unsigned foo(unsigned x, unsigned y) { if (x != 0) y--; return y; } before: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] sbbl %eax, %eax ## encoding: [0x19,0xc0] notl %eax ## encoding: [0xf7,0xd0] addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08] ret ## encoding: [0xc3] after: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] adcl $-1, %eax ## encoding: [0x83,0xd0,0xff] ret ## encoding: [0xc3] llvm-svn: 122455
* Fix a bug in ReduceLoadWidth that wasn't handling extendingChris Lattner2010-12-221-1/+4
| | | | | | | | | | | | | | | | | | | | | loads properly. We miscompiled the testcase into: _test: ## @test movl $128, (%rdi) movzbl 1(%rdi), %eax ret Now we get a proper: _test: ## @test movl $128, (%rdi) movsbl (%rdi), %eax movzbl %ah, %eax ret This fixes PR8757. llvm-svn: 122392
* more cleanups, move a check for "roundedness" earlier to rejectChris Lattner2010-12-221-14/+20
| | | | | | unhanded cases faster and simplify code. llvm-svn: 122391
* reduce indentation and improve comments, no functionality change.Chris Lattner2010-12-221-51/+53
| | | | llvm-svn: 122389
* In DelayForLiveRegsBottomUp, handle instructions that read and writeAndrew Trick2010-12-211-15/+4
| | | | | | | the same physical register. Simplifies the fix from the previous checkin r122211. llvm-svn: 122370
* whitespaceAndrew Trick2010-12-211-42/+42
| | | | llvm-svn: 122368
* Reapply 122353-122355 with fixes. 122354 was wrong;Dale Johannesen2010-12-211-4/+31
| | | | | | | | the shift type was needed one place, the shift count type another. The transform in 123555 had the same problem. llvm-svn: 122366
* Revert 122353-122355 for the moment, they broke stuff.Dale Johannesen2010-12-211-29/+3
| | | | llvm-svn: 122360
* Add a new transform to DAGCombiner.Dale Johannesen2010-12-211-0/+26
| | | | llvm-svn: 122355
* Get the type of a shift from the shift, not from its shiftDale Johannesen2010-12-211-1/+1
| | | | | | | | count operand. These should be the same but apparently are not always, and this is cleaner anyway. This improves the code in an existing test. llvm-svn: 122354
* Shift by the word size is invalid IR; don't create it.Dale Johannesen2010-12-211-2/+2
| | | | llvm-svn: 122353
* fix some typosChris Lattner2010-12-211-2/+1
| | | | llvm-svn: 122349
* Fix indentation, add comment.Stuart Hastings2010-12-211-4/+6
| | | | llvm-svn: 122345
* Missing logic for nested CALLSEQ_START/END.Stuart Hastings2010-12-211-2/+5
| | | | llvm-svn: 122342
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-2112-60/+60
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* improve "cannot yet select" errors a trivial amount: nowChris Lattner2010-12-211-1/+1
| | | | | | they are just as useless, but at least a bit more gramatical llvm-svn: 122305
* Cosmetic changes.Dale Johannesen2010-12-201-2/+2
| | | | llvm-svn: 122259
* implement type legalization promotion support for SMULO and UMULO, giving Chris Lattner2010-12-201-5/+48
| | | | | | | | ARM (and other 32-bit-only) targets support for i8 and i16 overflow multiplies. The generated code isn't great, but this at least fixes CodeGen/Generic/overflow.ll when running on ARM hosts. llvm-svn: 122221
* Fix a bug in the scheduler's handling of "unspillable" vregs.Chris Lattner2010-12-201-1/+14
| | | | | | | | | | | | | | | | | | Imagine we see: EFLAGS = inst1 EFLAGS = inst2 FLAGS gpr = inst3 EFLAGS Previously, we would refuse to schedule inst2 because it clobbers the EFLAGS of the predecessor. However, it also uses the EFLAGS of the predecessor, so it is safe to emit. SDep edges ensure that the right order happens already anyway. This fixes 2 testsuite crashes with the X86 patch I'm going to commit next. llvm-svn: 122211
* the result of CheckForLiveRegDef is dead, remove it.Chris Lattner2010-12-201-12/+8
| | | | llvm-svn: 122209
* reduce indentation, no functionality change.Chris Lattner2010-12-201-24/+25
| | | | llvm-svn: 122208
* Add missing standard headers. Patch by Joerg Sonnenberger!Nick Lewycky2010-12-191-0/+1
| | | | llvm-svn: 122193
* teach MaskedValueIsZero how to analyze ADDE. This isChris Lattner2010-12-191-2/+13
| | | | | | | enough to teach it that ADDE(0,0) is known 0 except the low bit, for example. llvm-svn: 122191
* fix PR8642: if a critical edge has a PHI value that can trap,Chris Lattner2010-12-191-0/+41
| | | | | | | isel is *required* to split the edge. PHI values get evaluated on the edge, not in their predecessor block. llvm-svn: 122170
* Fix a DAGCombiner crash when folding binary vector operations with constantBob Wilson2010-12-171-16/+9
| | | | | | | BUILD_VECTOR operands where the element type is not legal. I had previously changed this code to insert TRUNCATE operations, but that was just wrong. llvm-svn: 122102
* Add a transform to DAG Combiner. This improves theDale Johannesen2010-12-171-0/+20
| | | | | | | code for the case where 32-bit divide by constant is turned into 64-bit multiply by constant. 8771012. llvm-svn: 122090
* Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson2010-12-171-3/+1
| | | | | | Radar 8776599 llvm-svn: 122018
* take care of some todos, transforming [us]mul_lohi into Chris Lattner2010-12-151-2/+46
| | | | | | a wider mul if the wider mul is legal. llvm-svn: 121848
* when transforming a MULHS into a wider MUL, there is no need to SRA theChris Lattner2010-12-151-1/+1
| | | | | | result, the top bits are truncated off anyway, just use SRL. llvm-svn: 121846
* Add a couple dag combines to transform mulhi/mullo into a wider multiplyChris Lattner2010-12-131-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. llvm-svn: 121696
* reduce indentation by using continue, no functionality change.Chris Lattner2010-12-131-38/+41
| | | | llvm-svn: 121662
* Catch attempts to remove a deleted node from the CSE maps. Better toDuncan Sands2010-12-121-3/+2
| | | | | | | catch this here rather than later after accessing uninitialized memory etc. Fires when compiling the testcase in PR8237. llvm-svn: 121635
* Initial support for nested CALLSEQ_START/CALLSEQ_END constructs in LegalizeDAG.Stuart Hastings2010-12-091-8/+24
| | | | | | Necessary for byval support on ARM. Radar 7662569. llvm-svn: 121412
* 80-col fixups.Eric Christopher2010-12-091-9/+15
| | | | llvm-svn: 121356
* Reword comment slightly.Eric Christopher2010-12-081-1/+1
| | | | llvm-svn: 121293
* PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad2010-12-076-69/+59
| | | | | | | | zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
* If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG ↵Devang Patel2010-12-062-23/+14
| | | | | | message instead of creating DBG_VALUE for undefined value in reg0. llvm-svn: 121059
* Remove unneeded zero arrays.Benjamin Kramer2010-12-042-4/+2
| | | | llvm-svn: 120910
* PR5207: Rename overloaded APInt methods set(), clear(), flip() toJay Foad2010-12-013-7/+7
| | | | | | setAllBits(), setBit(unsigned), etc. llvm-svn: 120564
* Enable sibling call optimization of libcalls which are expanded duringEvan Cheng2010-11-301-6/+17
| | | | | | | | | | | legalization time. Since at legalization time there is no mapping from SDNode back to the corresponding LLVM instruction and the return SDNode is target specific, this requires a target hook to check for eligibility. Only x86 and ARM support this form of sibcall optimization right now. rdar://8707777 llvm-svn: 120501
* add TLI support indicating that jumps are more expensive than logical operationsChris Lattner2010-11-302-1/+4
| | | | | | and use this to disable a specific optimization. Patch by Micah Villmow! llvm-svn: 120435
* PR5207: Make APInt::set(), APInt::clear() and APInt::flip() return void.Jay Foad2010-11-301-2/+3
| | | | llvm-svn: 120413
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