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* Shift types need to match.Bill Wendling2009-01-201-8/+9
| | | | llvm-svn: 62571
* Fix a dagcombine to not generate loads of non-round integer types,Dan Gohman2009-01-201-1/+1
| | | | | | | as its comment says, even in the case where it will be generating extending loads. This fixes PR3216. llvm-svn: 62557
* Verify debug info.Devang Patel2009-01-192-9/+9
| | | | llvm-svn: 62545
* Remove SDNode's virtual destructor. This makes it impossible forDan Gohman2009-01-191-53/+14
| | | | | | | | | | | | | | SDNode subclasses to keep state that requires non-trivial destructors, however it was already effectively impossible, since the destructor isn't actually ever called. There currently aren't any SDNode subclasses affected by this, and in general it's desireable to keep SDNode objects light-weight. This eliminates the last virtual member function in the SDNode class, so it eliminates the need for a vtable pointer, making SDNode smaller. llvm-svn: 62539
* Fix SelectionDAG::ReplaceAllUsesWith to behave correctly whenDan Gohman2009-01-192-16/+39
| | | | | | | | | | | | | uses are added to the From node while it is processing From's use list, because of automatic local CSE. The fix is to avoid visiting any new uses. Fix a few places in the DAGCombiner that assumed that after a RAUW call, the From node has no users and may be deleted. This fixes PR3018. llvm-svn: 62533
* Few targets like PIC16 wants libcall generation for illegal type i16.Sanjiv Gupta2009-01-182-4/+16
| | | | llvm-svn: 62467
* Simplify extract element based on comments from Duncan Sands.Mon P Wang2009-01-181-7/+3
| | | | llvm-svn: 62459
* Simplify extract element of a scalar to vector.Mon P Wang2009-01-171-5/+13
| | | | llvm-svn: 62383
* Instead of adding dependence edges between terminator instructionsDan Gohman2009-01-162-9/+10
| | | | | | | | | | | | | | and every other instruction in their blocks to keep the terminator instructions at the end, teach the post-RA scheduler how to operate on ranges of instructions, and exclude terminators from the range of instructions that get scheduled. Also, exclude mid-block labels, such as EH_LABEL instructions, and schedule code before them separately from code after them. This fixes problems with the post-RA scheduler moving code past EH_LABELs. llvm-svn: 62366
* Use the getNode() accessor instead of accessing the NodeDan Gohman2009-01-161-1/+1
| | | | | | member directly, which is private as of r55504. llvm-svn: 62364
* new nodes should be added to the worklist, not old nodes.Chris Lattner2009-01-161-1/+2
| | | | llvm-svn: 62359
* CreateVirtualRegisters does trivial copy coalescing. If a node def is used ↵Evan Cheng2009-01-162-56/+63
| | | | | | by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. llvm-svn: 62356
* Registry.h should not depend on CommandLine.h.Mikhail Glushenkov2009-01-161-0/+1
| | | | | | | Split Support/Registry.h into two files so that we have less to recompile every time CommandLine.h is changed. llvm-svn: 62312
* Delete trailing whitespace.Mikhail Glushenkov2009-01-161-234/+234
| | | | llvm-svn: 62307
* Initial hazard recognizer support in post-pass scheduling. This includesDan Gohman2009-01-161-1/+1
| | | | | | | a new toy hazard recognizier heuristic which attempts to direct the scheduler to avoid clumping large groups of loads or stores too densely. llvm-svn: 62291
* Validate dbg_* intrinsics before lowering them.Devang Patel2009-01-152-10/+10
| | | | llvm-svn: 62286
* Added missing support to widen an operand from a bit convert.Mon P Wang2009-01-152-0/+32
| | | | llvm-svn: 62285
* Generalize the HazardRecognizer interface so that it can be usedDan Gohman2009-01-152-23/+11
| | | | | | | to support MachineInstr-based scheduling in addition to SDNode-based scheduling. llvm-svn: 62284
* Add the private linkage.Rafael Espindola2009-01-151-1/+1
| | | | llvm-svn: 62279
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-157-66/+51
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Make getWidenVectorType const; this file was missed in theDan Gohman2009-01-151-1/+1
| | | | | | previous commit. llvm-svn: 62266
* More consts on TargetLowering references.Dan Gohman2009-01-154-10/+9
| | | | llvm-svn: 62262
* Use const with TargetLowering references in a few more places.Dan Gohman2009-01-152-5/+7
| | | | llvm-svn: 62260
* minor refactoring: use a more specific APIGabor Greif2009-01-151-2/+3
| | | | llvm-svn: 62256
* Removoe MachineModuleInfo methods (and related DebugInfoDesc class ↵Devang Patel2009-01-131-1/+1
| | | | | | hierarchy) that were used to handle debug info. llvm-svn: 62199
* Undo previous checkin.Devang Patel2009-01-131-3/+2
| | | | llvm-svn: 62190
* Use dwarf writer to decide whether the module has debug info or not.Devang Patel2009-01-131-2/+3
| | | | llvm-svn: 62184
* The list-td and list-tdrr schedulers don't yet support physregDan Gohman2009-01-132-2/+10
| | | | | | | | | | | scheduling dependencies. Add assertion checks to help catch this. It appears the Mips target defaults to list-td, and it has a regression test that uses a physreg dependence. Such code was liable to be miscompiled, and now evokes an assertion failure. llvm-svn: 62177
* When replacing uses and the same node is reachedDuncan Sands2009-01-131-16/+9
| | | | | | | | via two paths, process it once not twice, d'oh! Analysis, testcase and original patch thanks to Mon Ping Wang. llvm-svn: 62169
* Fix some typos. Also, the WidenedVectors mapDuncan Sands2009-01-132-9/+20
| | | | | | was not being cleaned by ExpungeNode. llvm-svn: 62167
* Correct a comment - this is not a sign extension.Duncan Sands2009-01-131-1/+1
| | | | llvm-svn: 62166
* Use DebugInfo interface to lower dbg_* intrinsics.Devang Patel2009-01-136-56/+69
| | | | llvm-svn: 62127
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-124-14/+15
| | | | | | suggested by Chris. llvm-svn: 62099
* Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical ↵Evan Cheng2009-01-124-61/+84
| | | | | | | | register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet. llvm-svn: 62074
* CheckForPhysRegDependency should not return copy cost. It's not used. No ↵Evan Cheng2009-01-111-9/+4
| | | | | | functionality change. llvm-svn: 62036
* Duplicated node may produce a non-physical register def.Evan Cheng2009-01-091-3/+5
| | | | llvm-svn: 62015
* Minor debug output tweak.Evan Cheng2009-01-091-2/+2
| | | | llvm-svn: 62005
* Request DwarfWriter. This will be used to handle dbg_* intrinsics.Devang Patel2009-01-092-2/+7
| | | | llvm-svn: 61999
* Removed trailing whitespace from Makefiles.Misha Brukman2009-01-091-2/+2
| | | | llvm-svn: 61991
* Remove redundant 'else's. No functionality change.Dan Gohman2009-01-071-7/+6
| | | | llvm-svn: 61891
* Fix a bug in ComputeLinearIndex computation handling multi-levelDan Gohman2009-01-061-1/+3
| | | | | | | | aggregate types. Don't increment the current index after reaching the end of a struct, as it will already be pointing at one-past-the end. This fixes PR3288. llvm-svn: 61828
* Update these argument lists for the isNormalMemoryDan Gohman2009-01-061-3/+6
| | | | | | argument. This doesn't affect current functionality. llvm-svn: 61779
* Use a latency value of 0 for the artificial edges inserted byDan Gohman2009-01-061-1/+1
| | | | | | | | | | | | AddPseudoTwoAddrDeps. This lets the scheduling infrastructure avoid recalculating node heights. In very large testcases this was a major bottleneck. Thanks to Roman Levenstein for finding this! As a side effect, fold-pcmpeqd-0.ll is now scheduled better and it no longer requires spilling on x86-32. llvm-svn: 61778
* TargetLowering.h #includes SelectionDAGNodes.h, so it doesn't need itsDan Gohman2009-01-051-2/+0
| | | | | | | own OpActionsCapacity magic number; it can just use ISD::BUILTIN_OP_END, as long as it takes care to round up when needed. llvm-svn: 61733
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-052-3/+0
| | | | llvm-svn: 61715
* squash warnings.Devang Patel2009-01-051-0/+1
| | | | llvm-svn: 61707
* Fix a DAGCombiner abort on an invalid shift count constant. This fixes PR3250.Dan Gohman2009-01-031-0/+2
| | | | llvm-svn: 61613
* CommuteNodesToReducePressure() is now removed.Dan Gohman2009-01-031-1/+0
| | | | llvm-svn: 61612
* Remove the code from the scheduler that commuted two-addressDan Gohman2009-01-032-71/+0
| | | | | | | | | | | | | | instructions to avoid copies, because TwoAddressInstructionPass also does this optimization. The scheduler's version didn't account for live-out values, which resulted in spurious commutes and missed opportunities. Now, TwoAddressInstructionPass handles all the opportunities, instead of just those that the scheduler missed. The result is usually the same, though there are occasional trivial differences resulting from the avoidance of spurious commutes. llvm-svn: 61611
* Factorize (and generalize) the code promoting SELECTDuncan Sands2009-01-013-152/+105
| | | | | | | and BRCOND conditions. Reorder a few methods while there. llvm-svn: 61547
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