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* Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics.Bill Wendling2012-01-312-91/+0
| | | | llvm-svn: 149331
* Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copyBill Wendling2012-01-312-53/+0
| | | | | | | over the catch information. The catch information is now tacked to the invoke instruction. llvm-svn: 149326
* Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. ↵Eli Friedman2012-01-311-7/+9
| | | | | | Not committing a testcase because I think it will be too fragile. llvm-svn: 149315
* continue making the world safe for ConstantDataVector. At this point,Chris Lattner2012-01-271-1/+1
| | | | | | | we should (theoretically optimize and codegen ConstantDataVector as well as ConstantVector. llvm-svn: 149116
* eliminate the Constant::getVectorElements method. There are better (andChris Lattner2012-01-261-13/+4
| | | | | | | more robust) ways to do what it was doing now. Also, add static methods for decoding a ShuffleVector mask. llvm-svn: 149028
* use ConstantVector::getSplat in a few places.Chris Lattner2012-01-251-1/+1
| | | | llvm-svn: 148929
* Use the right method to get the # elements in a CDS.Chris Lattner2012-01-251-1/+1
| | | | llvm-svn: 148897
* add more support for ConstantDataSequentialChris Lattner2012-01-241-2/+19
| | | | llvm-svn: 148802
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-206-21/+5
| | | | llvm-svn: 148578
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-184-2/+22
| | | | | | | | | | | This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. llvm-svn: 148436
* Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem2012-01-181-2/+4
| | | | | | vector type to another, we must not bitcast the result if one type is widened while the other is promoted. llvm-svn: 148383
* Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper2012-01-181-7/+12
| | | | | | TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE llvm-svn: 148377
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-171-4/+35
| | | | llvm-svn: 148337
* Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector ↵Craig Topper2012-01-171-4/+8
| | | | | | type. llvm-svn: 148297
* Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ↵Pete Cooper2012-01-171-2/+3
| | | | | | checked for legalisation llvm-svn: 148275
* Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie2012-01-161-2/+0
| | | | | | unused variables). llvm-svn: 148230
* Changed intrinsic ID operand to a target constant as its not used in any ↵Pete Cooper2012-01-161-1/+1
| | | | | | arithmetic so should not be checked in legalisation llvm-svn: 148228
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-151-5/+22
| | | | | | | | | | | We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer2012-01-151-7/+5
| | | | | | CodeGen. llvm-svn: 148218
* DAGCombiner: Deduplicate code.Benjamin Kramer2012-01-151-24/+14
| | | | llvm-svn: 148217
* Truncate of undef is just undef of smaller size.Craig Topper2012-01-151-5/+6
| | | | llvm-svn: 148205
* DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng2012-01-131-9/+44
| | | | | | | | | | | | | | | | overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 llvm-svn: 148086
* Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to ↵Pete Cooper2012-01-121-0/+18
| | | | | | | | Promote for those operations. Sorry, no test case yet llvm-svn: 148050
* Allow targets to select source order pre-RA scheduler.Evan Cheng2012-01-121-1/+2
| | | | llvm-svn: 148033
* On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem2012-01-111-5/+23
| | | | | | | | | | are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. llvm-svn: 147964
* Teach the X86 instruction selection to do some heroic transforms toChandler Carruth2012-01-111-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. llvm-svn: 147936
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-101-0/+1
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-105-13/+0
| | | | llvm-svn: 147855
* Fix a bug in the legalization of shuffle vectors. When we emulate shuffles ↵Nadav Rotem2012-01-101-1/+3
| | | | | | using BUILD_VECTORS we may be using a BV of different type. Make sure to cast it back. llvm-svn: 147851
* Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper2012-01-071-4/+4
| | | | llvm-svn: 147733
* Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper2012-01-071-2/+51
| | | | | | subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. llvm-svn: 147728
* Add comment.Chad Rosier2012-01-061-0/+4
| | | | llvm-svn: 147696
* Prevent a DAGCombine from firing where there are two uses ofChandler Carruth2012-01-051-1/+3
| | | | | | | | | a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. llvm-svn: 147604
* Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper2012-01-041-11/+24
| | | | | | are commuted in the shuffle mask. llvm-svn: 147527
* Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper2012-01-041-2/+50
| | | | llvm-svn: 147525
* Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner2012-01-031-9/+21
| | | | | | | | | | | | | | | | | | Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. llvm-svn: 147502
* Fix incorrect widening of the bitcast sdnode in case the incoming operand is ↵Nadav Rotem2012-01-031-0/+6
| | | | | | integer-promoted. llvm-svn: 147484
* Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson2012-01-031-8/+0
| | | | | | Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-031-6/+50
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147445
* Revert 147399. It broke CodeGen/ARM/vext.ll.Rafael Espindola2012-01-011-39/+5
| | | | llvm-svn: 147400
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-011-5/+39
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147399
* PR11662.Nadav Rotem2011-12-281-1/+5
| | | | | | Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. llvm-svn: 147309
* Make sure DAGCombiner doesn't introduce multiple loads from the same memory ↵Eli Friedman2011-12-261-1/+23
| | | | | | location. PR10747, part 2. llvm-svn: 147283
* Fix a typo in the widening of vectors in PromoteIntRes. Patch by Shemer Anat.Nadav Rotem2011-12-251-2/+2
| | | | llvm-svn: 147272
* drop unneeded config.h includesDylan Noblesmith2011-12-221-1/+0
| | | | llvm-svn: 147197
* Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.Jakub Staszak2011-12-202-3/+4
| | | | llvm-svn: 146986
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Add basic generic CodeGen support for half.Dan Gohman2011-12-201-10/+21
| | | | llvm-svn: 146927
* Allow inlining of functions with returns_twice calls, if they have theJoerg Sonnenberger2011-12-181-1/+1
| | | | | | attribute themselve. llvm-svn: 146851
* Update DebugLoc while merging nodes at -O0.Devang Patel2011-12-152-6/+21
| | | | | | Patch by Kyriakos Georgiou! llvm-svn: 146670
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