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* If FastISel is run and it has known DebugLoc then use it.Devang Patel2009-04-162-3/+7
| | | | llvm-svn: 69253
* If location where the function was inlined is not know then do not emit ↵Devang Patel2009-04-161-5/+11
| | | | | | debug info describing inlinied region. llvm-svn: 69252
* Add DISubprogram is not null check.Devang Patel2009-04-151-2/+4
| | | | | | This fixes test/CodeGen//2009-01-21-invalid-debug-info.m test case. llvm-svn: 69210
* Generalize one of the SelectionDAG::ReplaceAllUsesWith overloadsDan Gohman2009-04-152-9/+10
| | | | | | | | to support replacing a node with another that has a superset of the result types. Use this instead of calling ReplaceAllUsesOfValueWith for each value. llvm-svn: 69209
* Construct and emit DW_TAG_inlined_subroutine DIEs for inlined subroutine ↵Devang Patel2009-04-151-14/+28
| | | | | | scopes (only in FastISel mode). llvm-svn: 69116
* When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REGDan Gohman2009-04-141-20/+19
| | | | | | | | | | | | operator is used by a CopyToReg to export the value to a different block, don't reuse the CopyToReg's register for the subreg operation result if the register isn't precisely the right class for the subreg operation. Also, rename the h-registers.ll test, now that there are more than one. llvm-svn: 69087
* Do not force asm's to be chained if they don't touchDale Johannesen2009-04-141-0/+3
| | | | | | | memory and aren't volatile. This was interfering with good scheduling. llvm-svn: 69008
* Make these errors more noticable in build logs.Daniel Dunbar2009-04-131-5/+5
| | | | llvm-svn: 68998
* Change SelectionDAG type legalization to allow BUILD_VECTOR operands to beBob Wilson2009-04-135-31/+78
| | | | | | | | | | | | | | | | | | | | | | | | promoted to legal types without changing the type of the vector. This is following a suggestion from Duncan (http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-February/019923.html). The transformation that used to be done during type legalization is now postponed to DAG legalization. This allows the BUILD_VECTORs to be optimized and potentially handled specially by target-specific code. It turns out that this is also consistent with an optimization done by the DAG combiner: a BUILD_VECTOR and INSERT_VECTOR_ELT may be combined by replacing one of the BUILD_VECTOR operands with the newly inserted element; but INSERT_VECTOR_ELT allows its scalar operand to be larger than the element type, with any extra high bits being implicitly truncated. The result is a BUILD_VECTOR where one of the operands has a type larger the the vector element type. Any code that operates on BUILD_VECTORs may now need to be aware of the potential type discrepancy between the vector element type and the BUILD_VECTOR operands. This patch updates all of the places that I could find to handle that case. llvm-svn: 68996
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-132-14/+13
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Refactor some code in SelectionDAGLegalize::ExpandBUILD_VECTOR.Bob Wilson2009-04-131-24/+19
| | | | llvm-svn: 68981
* Right now, Debugging information to encode scopes (DW_TAG_lexical_block) ↵Devang Patel2009-04-132-18/+16
| | | | | | | | relies on DBG_LABEL. Unfortunately this intefers with the quality of optimized code. This patch updates dwarf writer to encode scoping information in DWARF only in FastISel mode. llvm-svn: 68973
* Reapply 68847.Devang Patel2009-04-132-3/+37
| | | | | | Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default. llvm-svn: 68964
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-132-75/+170
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* make UpdateValueMap handle the possiblity that we could beChris Lattner2009-04-121-1/+1
| | | | | | copying into the right register, avoiding a copy. llvm-svn: 68889
* optimize FastISel::UpdateValueMap to avoid duplicate map lookups,Chris Lattner2009-04-121-7/+12
| | | | | | and make it return the assigned register. llvm-svn: 68888
* Revert r68847. It breaks the build on non-Darwin targets, with this messageDan Gohman2009-04-112-37/+3
| | | | | | | from the assembler: Error: unknown pseudo-op: `.debug_inlined' llvm-svn: 68863
* Keep track of inlined functions and their locations. This information is ↵Devang Patel2009-04-112-3/+37
| | | | | | | | collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.) Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section. llvm-svn: 68847
* Clean up a bunch of whitespace issues and fix a comment typo.Bob Wilson2009-04-101-72/+74
| | | | | | No functional changes. llvm-svn: 68808
* Now that register classes have names, include the name in debug output.Dan Gohman2009-04-101-2/+4
| | | | llvm-svn: 68786
* Remove the obsolete SelectionDAG::getNodeValueTypes and simplifyDan Gohman2009-04-094-57/+41
| | | | | | code that uses it by using SelectionDAG::getVTList instead. llvm-svn: 68744
* Silence unused variable warning.Devang Patel2009-04-091-1/+1
| | | | llvm-svn: 68735
* llvm.dbg.func_start also defines beginning of function scope.Devang Patel2009-04-091-7/+3
| | | | llvm-svn: 68727
* Generalize ExtendUsesToFormExtLoad to be usable for ANY_EXTEND,Dan Gohman2009-04-092-45/+78
| | | | | | | | | | | | | | | in addition to ZERO_EXTEND and SIGN_EXTEND. Fix a bug in the way it checked for live-out values, and simplify the way it find users by using SDNode::use_iterator's (relatively) new features. Also, make it slightly more permissive on targets with free truncates. In SelectionDAGBuild, avoid creating ANY_EXTEND nodes that are larger than necessary. If the target's SwitchAmountTy has enough bits, use it. This exposes the truncate to optimization early, enabling more optimizations. llvm-svn: 68670
* Don't copy the operand of a SwitchInst into virtual registers asDan Gohman2009-04-091-3/+13
| | | | | | | | | | eagerly. This helps avoid CopyToReg nodes in some cases where they aren't needed, and also helps subsequent optimizer heuristics in cases where the extra nodes would cause the node to appear to have multiple results. This doesn't have a significant impact currently; it'll help an upcoming change. llvm-svn: 68667
* Soft float support for FREM.Duncan Sands2009-04-082-0/+14
| | | | llvm-svn: 68614
* Soft float support for undef. Reported by Xerxes Rånby.Duncan Sands2009-04-082-0/+6
| | | | llvm-svn: 68607
* Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman2009-04-082-9/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
* Revert prev. patch for now.Devang Patel2009-04-071-4/+6
| | | | llvm-svn: 68569
* Right now DBG_LABEL are required for llvm.dbg.region_start and ↵Devang Patel2009-04-071-6/+4
| | | | | | llvm.dbg.region_end in non-fast mode also. llvm-svn: 68559
* Don't attempt to handle aggregate argument values in FastISel; letDan Gohman2009-04-071-1/+5
| | | | | | SelectionDAG do those. This fixes PR3955. llvm-svn: 68546
* Fix a TargetLowering optimization so that it doesn't duplicateDan Gohman2009-04-031-0/+1
| | | | | | loads when an input node has multiple uses. llvm-svn: 68398
* Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.Dan Gohman2009-04-032-20/+0
| | | | | | | Note that these are distinct from TargetInstrInfo::INSERT_SUBREG and TargetInstrInfo::EXTRACT_SUBREG, which are used. llvm-svn: 68355
* To convert the StopPoint insn into an assembler directive by ISel, we need ↵Sanjiv Gupta2009-04-021-0/+4
| | | | | | to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize. llvm-svn: 68329
* Fully general expansion of integer shift of any size.Evan Cheng2009-03-312-3/+81
| | | | llvm-svn: 68134
* Minor top-level comment fix.Dan Gohman2009-03-311-1/+1
| | | | llvm-svn: 68113
* Fix live-out reg logic to not insert over-aggressive AssertZExtDan Gohman2009-03-311-3/+3
| | | | | | instructions. This fixes lua. llvm-svn: 68083
* Fix PR3899: add support for extracting floats from vectorsDuncan Sands2009-03-293-0/+22
| | | | | | | when using -soft-float. Based on a patch by Jakob Stoklund Olesen. llvm-svn: 67996
* Make check in CheckTailCallReturnConstraints for ignorable instructions betweenArnold Schwaighofer2009-03-281-18/+32
| | | | | | | a CALL and a RET node more generic. Add a test for tail calls with a void return. llvm-svn: 67943
* Enable tail call optimization for functions that return a struct (bug 3664) ↵Arnold Schwaighofer2009-03-281-0/+24
| | | | | | and for functions that return types that need extending (e.g i1). llvm-svn: 67934
* Optimize some 64-bit multiplication by constants into two lea's or one lea + ↵Evan Cheng2009-03-281-8/+8
| | | | | | | | | | | | | | | | | shl since imulq is slow (latency 5). e.g. x * 40 => shlq $3, %rdi leaq (%rdi,%rdi,4), %rax This has the added benefit of allowing more multiply to be folded into addressing mode. e.g. a * 24 + b => leaq (%rdi,%rdi,2), %rax leaq (%rsi,%rax,8), %rax llvm-svn: 67917
* Fix what surely must be a copy+pasto.Dan Gohman2009-03-271-2/+2
| | | | llvm-svn: 67881
* Initialize LiveOutInfo's APInt members to zero, as APInt'sDan Gohman2009-03-271-1/+1
| | | | | | | default constructor produces an uninitialized APInt. This fixes PR3896. llvm-svn: 67879
* Pull transform from target-dependent code into target-independent code.Bill Wendling2009-03-261-0/+49
| | | | llvm-svn: 67742
* Revert 67132. This is breaking some objective-c apps.Evan Cheng2009-03-251-3/+13
| | | | | | Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext. llvm-svn: 67701
* When optimizing with debug info, don't keep theDale Johannesen2009-03-251-4/+5
| | | | | | | | stoppoint nodes around until Legalize; doing this imposed an ordering on a sequence of loads that came from different lines, interfering with scheduling. llvm-svn: 67692
* more tidying: name the components of PhysReg in the case whenChris Lattner2009-03-241-8/+9
| | | | | | the target constraint specifies a specific physreg. llvm-svn: 67618
* Tidy a bit more.Chris Lattner2009-03-241-3/+3
| | | | llvm-svn: 67617
* simplify this code a bit now that "allocation to a vreg class" can neverChris Lattner2009-03-241-16/+13
| | | | | | fail. llvm-svn: 67616
* Minor compile-time optimization; don't bother checkingDan Gohman2009-03-241-1/+1
| | | | | | | canClobberPhysRegDefs if the successor node doesn't clobber any physical registers. llvm-svn: 67587
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