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* Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper2012-01-071-4/+4
| | | | llvm-svn: 147733
* Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper2012-01-071-2/+51
| | | | | | subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. llvm-svn: 147728
* Add comment.Chad Rosier2012-01-061-0/+4
| | | | llvm-svn: 147696
* Prevent a DAGCombine from firing where there are two uses ofChandler Carruth2012-01-051-1/+3
| | | | | | | | | a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. llvm-svn: 147604
* Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper2012-01-041-11/+24
| | | | | | are commuted in the shuffle mask. llvm-svn: 147527
* Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper2012-01-041-2/+50
| | | | llvm-svn: 147525
* Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner2012-01-031-9/+21
| | | | | | | | | | | | | | | | | | Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. llvm-svn: 147502
* Fix incorrect widening of the bitcast sdnode in case the incoming operand is ↵Nadav Rotem2012-01-031-0/+6
| | | | | | integer-promoted. llvm-svn: 147484
* Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson2012-01-031-8/+0
| | | | | | Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-031-6/+50
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147445
* Revert 147399. It broke CodeGen/ARM/vext.ll.Rafael Espindola2012-01-011-39/+5
| | | | llvm-svn: 147400
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-011-5/+39
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147399
* PR11662.Nadav Rotem2011-12-281-1/+5
| | | | | | Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. llvm-svn: 147309
* Make sure DAGCombiner doesn't introduce multiple loads from the same memory ↵Eli Friedman2011-12-261-1/+23
| | | | | | location. PR10747, part 2. llvm-svn: 147283
* Fix a typo in the widening of vectors in PromoteIntRes. Patch by Shemer Anat.Nadav Rotem2011-12-251-2/+2
| | | | llvm-svn: 147272
* drop unneeded config.h includesDylan Noblesmith2011-12-221-1/+0
| | | | llvm-svn: 147197
* Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.Jakub Staszak2011-12-202-3/+4
| | | | llvm-svn: 146986
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Add basic generic CodeGen support for half.Dan Gohman2011-12-201-10/+21
| | | | llvm-svn: 146927
* Allow inlining of functions with returns_twice calls, if they have theJoerg Sonnenberger2011-12-181-1/+1
| | | | | | attribute themselve. llvm-svn: 146851
* Update DebugLoc while merging nodes at -O0.Devang Patel2011-12-152-6/+21
| | | | | | Patch by Kyriakos Georgiou! llvm-svn: 146670
* Don't try to form FGETSIGN after legalization; it is possible in some cases, ↵Eli Friedman2011-12-151-1/+2
| | | | | | but the existing code can't do it correctly. PR11570. llvm-svn: 146630
* Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. ↵Owen Anderson2011-12-151-0/+22
| | | | | | These are already marked as illegal by default. llvm-svn: 146623
* Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow.Eli Friedman2011-12-141-0/+5
| | | | llvm-svn: 146548
* [fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle Chad Rosier2011-12-131-103/+0
| | | | | | instructions that define aggregate types. llvm-svn: 146492
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-137-23/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* [fast-isel] Guard "exhastive" fast-isel output with -fast-isel-verbose2.Chad Rosier2011-12-131-1/+6
| | | | llvm-svn: 146453
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-121-1/+0
| | | | llvm-svn: 146409
* [fast-isel] SelectInsertValue seems to be causing miscompiles for ARM. ↵Chad Rosier2011-12-101-0/+1
| | | | | | Disable while I investigate. llvm-svn: 146331
* Typo.Chad Rosier2011-12-101-1/+1
| | | | llvm-svn: 146327
* [fast-isel] Add support for selecting insertvalue.Chad Rosier2011-12-091-0/+102
| | | | | | rdar://10530851 llvm-svn: 146276
* Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.Eli Friedman2011-12-091-4/+3
| | | | llvm-svn: 146219
* Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter ↵Owen Anderson2011-12-083-15/+43
| | | | | | can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. llvm-svn: 146193
* Add rather verbose stats for fast-isel failures.Chad Rosier2011-12-081-0/+153
| | | | llvm-svn: 146186
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-082-10/+67
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
* Fix a bug in the integer-promotion of bitcast operations on vector types.Nadav Rotem2011-12-081-1/+1
| | | | | | | We must not issue a bitcast operation for integer-promotion of vector types, because the location of the values in the vector may be different. llvm-svn: 146150
* Make sure we correctly set LiveRegGens when a call is unscheduled. ↵Eli Friedman2011-12-071-1/+8
| | | | | | <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling. llvm-svn: 146087
* Fix an assertion in the scheduler. PR11386. No testcase included because ↵Eli Friedman2011-12-071-3/+2
| | | | | | it's rather delicate. llvm-svn: 146083
* These global variables aren't thread-safe, STATISTIC is. Andy Trick tells meNick Lewycky2011-12-071-66/+12
| | | | | | that he isn't using these any more, so just delete them. llvm-svn: 146076
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-072-2/+2
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this ↵Eli Friedman2011-12-071-1/+1
| | | | | | doesn't affect any in-tree target. llvm-svn: 146015
* Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves ↵Eli Friedman2011-12-071-13/+17
| | | | | | correctly. PR11494. llvm-svn: 145996
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-1/+2
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Add support for vectors of pointers.Nadav Rotem2011-12-051-1/+1
| | | | llvm-svn: 145801
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-024-45/+68
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* If fast-isel fails, remove dead instructions generated during the failed Chad Rosier2011-11-291-0/+27
| | | | | | attempt. llvm-svn: 145425
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-291-10/+0
| | | | llvm-svn: 145420
* Make SelectionDAG::InferPtrAlignment use llvm::ComputeMaskedBits instead of ↵Eli Friedman2011-11-281-18/+9
| | | | | | duplicating the logic for globals. Make llvm::ComputeMaskedBits handle GlobalVariables slightly more aggressively, to match what InferPtrAlignment knew how to do. llvm-svn: 145304
* Revert r145273 and fix in SelectionDAG::InferPtrAlignment() instead.Evan Cheng2011-11-282-27/+17
| | | | | | | | | | | Conservatively returns zero when the GV does not specify an alignment nor is it initialized. Previously it returns ABI alignment for type of the GV. However, if the type is a "packed" type, then the under-specified alignments is attached to the load / store instructions. In that case, the alignment of the type cannot be trusted. rdar://10464621 llvm-svn: 145300
* DAG combine should not increase alignment of loads / stores with alignment lessEvan Cheng2011-11-281-12/+26
| | | | | | | | | than ABI alignment. These are loads / stores from / to "packed" data structures. Their alignments are intentionally under-specified. rdar://10301431 llvm-svn: 145273
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