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* Teach DAG combine a number of tricks to simplify FMA expressions in ↵Owen Anderson2012-09-011-0/+64
| | | | | | fast-math mode. llvm-svn: 163051
* Fix typoMichael Liao2012-09-011-1/+1
| | | | llvm-svn: 163049
* Add MachineInstr::tieOperands, remove setIsTied().Jakob Stoklund Olesen2012-08-311-6/+2
| | | | | | | | | | | Manage tied operands entirely internally to MachineInstr. This makes it possible to change the representation of tied operands, as I will do shortly. The constraint that tied uses and defs must be in the same order was too restrictive. llvm-svn: 163021
* Don't enforce ordered inline asm operands.Jakob Stoklund Olesen2012-08-311-10/+0
| | | | | | | | | I was too optimistic, inline asm can have tied operands that don't follow the def order. Fixes PR13742. llvm-svn: 162998
* Take account of boolean vector contents when promoting a build vector from ↵Pete Cooper2012-08-301-1/+17
| | | | | | i1 to some other type. rdar://problem/12210060 llvm-svn: 162960
* Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by ↵Owen Anderson2012-08-301-1/+122
| | | | | | constants. This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants. llvm-svn: 162956
* Currently targets that do not support selects with scalar conditions and ↵Nadav Rotem2012-08-301-1/+65
| | | | | | | | | | | vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926
* Add FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be ↵Craig Topper2012-08-301-0/+1
| | | | | | expanded when it isn't legal. llvm-svn: 162894
* Add support for FMA to WidenVectorResult.Craig Topper2012-08-302-0/+14
| | | | llvm-svn: 162893
* Verify the order of tied operands in inline asm.Jakob Stoklund Olesen2012-08-291-0/+12
| | | | | | | | | | | | | | When there are multiple tied use-def pairs on an inline asm instruction, the tied uses must appear in the same order as the defs. It is possible to write an LLVM IR inline asm instruction that breaks this constraint, but there is no reason for a front end to emit the operands out of order. The gnu inline asm syntax specifies tied operands as a single read/write constraint "+r", so ouf of order operands are not possible. llvm-svn: 162878
* Set the isTied flags when building INLINEASM MachineInstrs.Jakob Stoklund Olesen2012-08-291-4/+21
| | | | | | | | For normal instructions, isTied() is set automatically by addOperand(), based on MCInstrDesc, but inline asm has tied operands outside the descriptor. llvm-svn: 162869
* Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen2012-08-281-18/+23
| | | | | | | | | | | | | | | These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. llvm-svn: 162733
* Fix bug 13532.Akira Hatanaka2012-08-281-1/+1
| | | | | | | | | In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without using any f64 operations if f64 is not a legal type. Patch by Stefan Kristiansson. llvm-svn: 162728
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-3/+2
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Avoid including explicit uses when counting SDNode imp-uses.Jakob Stoklund Olesen2012-08-241-3/+6
| | | | | | | It is legal to have a register node as an explicit operand, it shouldn't be counted as an implicit use. llvm-svn: 162591
* BranchProb: modify the definition of an edge in BranchProbabilityInfo to handleManman Ren2012-08-243-28/+60
| | | | | | | | | | | | | | the case of multiple edges from one block to another. A simple example is a switch statement with multiple values to the same destination. The definition of an edge is modified from a pair of blocks to a pair of PredBlock and an index into the successors. Also set the weight correctly when building SelectionDAG from LLVM IR, especially when converting a Switch. IntegersSubsetMapping is updated to calculate the weight for each cluster. llvm-svn: 162572
* Rejected 169195. As Duncan commented, bitcasting to proper type is wrong ↵Stepan Dyatkovskiy2012-08-221-23/+3
| | | | | | approach. We need to insert some valid TRANCATE node here. llvm-svn: 162354
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-222-5/+4
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Initialize SelectionDAGBuilder's Context in 'init', not in its constructor. TheRichard Smith2012-08-222-1/+2
| | | | | | | | SelectionDAG's 'init' has not been called when the SelectionDAGBuilder is constructed (in SelectionDAGISel's constructor), so this was previously always initialized with 0. llvm-svn: 162333
* Don't add CFG edges for redundant conditional branches.Jakob Stoklund Olesen2012-08-201-1/+4
| | | | | | | | | | | | | IR that hasn't been through SimplifyCFG can look like this: br i1 %b, label %r, label %r Make sure we don't create duplicate Machine CFG edges in this case. Fix the machine code verifier to accept conditional branches with a single CFG edge. llvm-svn: 162230
* Fixed DAGCombiner bug (found and localized by James Malloy):Stepan Dyatkovskiy2012-08-201-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DAGCombiner tries to optimise a BUILD_VECTOR by checking if it consists purely of get_vector_elts from one or two source vectors. If so, it either makes a concat_vectors node or a shufflevector node. However, it doesn't check the element type width of the underlying vector, so if you have this sequence: Node0: v4i16 = ... Node1: i32 = extract_vector_elt Node0 Node2: i32 = extract_vector_elt Node0 Node3: v16i8 = BUILD_VECTOR Node1, Node2, ... It will attempt to: Node0: v4i16 = ... NewNode1: v16i8 = concat_vectors Node0, ... Where this is actually invalid because the element width is completely different. This causes an assertion failure on DAG legalization stage. Fix: If output item type of BUILD_VECTOR differs from input item type. Make concat_vectors based on input element type and then bitcast it to the output vector type. So the case described above will transformed to: Node0: v4i16 = ... NewNode1: v8i16 = concat_vectors Node0, ... NewNode2: v16i8 = bitcast NewNode1 llvm-svn: 162195
* Make atomic load and store of pointers work. Tighten verification of atomic ↵Eli Friedman2012-08-171-2/+2
| | | | | | | | | operations so other unexpected operations don't slip through. Based on patch by Logan Chien. PR11786/PR13186. llvm-svn: 162146
* TargetLowering: Use the large shift amount during legalize types. The ↵Benjamin Kramer2012-08-171-3/+3
| | | | | | legalizer may call us with an overly large type. llvm-svn: 162101
* Add a roundToIntegral method to APFloat, which can be parameterized over ↵Owen Anderson2012-08-132-0/+60
| | | | | | various rounding modes. Use this to implement SelectionDAG constant folding of FFLOOR, FCEIL, and FTRUNC. llvm-svn: 161807
* Fix the legalization of ExtLoad on ARM. ExpandUnalignedLoad did not properly Nadav Rotem2012-08-091-3/+4
| | | | | | | handle the cases where the memory value type was illegal. PR 13111. llvm-svn: 161565
* Add SelectionDAG::getTargetIndex.Jakob Stoklund Olesen2012-08-074-0/+35
| | | | | | | This adds support for TargetIndex operands during isel. The meaning of these (index, offset, flags) operands is entirely defined by the target. llvm-svn: 161453
* Refactor and check "onlyReadsMemory" before optimizing builtins.Bob Wilson2012-08-032-83/+30
| | | | | | | | | This patch is mostly just refactoring a bunch of copy-and-pasted code, but it also adds a check that the call instructions are readnone or readonly. That check was already present for sin, cos, sqrt, log2, and exp2 calls, but it was missing for the rest of the builtins being handled in this code. llvm-svn: 161282
* Try to reduce the compile time impact of r161232.Bob Wilson2012-08-032-43/+59
| | | | | | | | | | | | The previous change caused fast isel to not attempt handling any calls to builtin functions. That included things like "printf" and caused some noticable regressions in compile time. I wanted to avoid having fast isel keep a separate list of functions that had to be kept in sync with what the code in SelectionDAGBuilder.cpp was handling. I've resolved that here by moving the list into TargetLibraryInfo. This is somewhat redundant in SelectionDAGBuilder but it will ensure that we keep things consistent. llvm-svn: 161263
* Fix memcmp code-gen to honor -fno-builtin.Bob Wilson2012-08-031-1/+1
| | | | | | | | | I noticed that SelectionDAGBuilder::visitCall was missing a check for memcmp in TargetLibraryInfo, so that it would use custom code for memcmp calls even with -fno-builtin. I also had to add a new -disable-simplify-libcalls option to llc so that I could write a test for this. llvm-svn: 161262
* Fall back to selection DAG isel for calls to builtin functions.Bob Wilson2012-08-032-3/+18
| | | | | | | | | | Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> llvm-svn: 161232
* Added FMA functionality to X86 target.Elena Demikhovsky2012-08-011-8/+20
| | | | llvm-svn: 161110
* Conform to LLVM coding style.Micah Villmow2012-07-311-2/+2
| | | | llvm-svn: 161061
* Don't generate ordered or unordered comparison operations if it is not legal ↵Micah Villmow2012-07-311-1/+2
| | | | | | to do so. llvm-svn: 161053
* Consider address spaces for hashing and CSEing DAG nodes. Otherwise two ↵Pete Cooper2012-07-301-0/+22
| | | | | | loads from different x86 segments but the same address would get CSEd llvm-svn: 160987
* Add a floor intrinsic.Dan Gohman2012-07-261-0/+5
| | | | llvm-svn: 160791
* Change llvm_unreachable in SplitVectorOperand to report_fatal_error. Keeps ↵Craig Topper2012-07-241-1/+3
| | | | | | release builds from crashing if code uses an intrinsic with an illegal type. llvm-svn: 160661
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
| | | | llvm-svn: 160621
* Fixed DAGCombine optimizations which generate select_cc for targetsNadav Rotem2012-07-231-33/+47
| | | | | | | | | | that do not support it (X86 does not lower select_cc). PR: 13428 Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160619
* Tidy up. Fix indentation and remove trailing whitespace.Craig Topper2012-07-231-16/+14
| | | | llvm-svn: 160617
* Change llvm_unreachable in SplitVectorResult to report_fatal_error. Keeps ↵Craig Topper2012-07-231-1/+2
| | | | | | release builds from crashing if code uses an intrinsic with an illegal type. For instance 256-bit AVX intrinsics without having AVX enabled. llvm-svn: 160616
* Replace some explicit compare loops with std::equal.Benjamin Kramer2012-07-191-7/+1
| | | | | | No functionality change. llvm-svn: 160501
* Fixed few warnings.Galina Kistanova2012-07-191-1/+1
| | | | llvm-svn: 160493
* Remove tabs.Bill Wendling2012-07-194-22/+24
| | | | llvm-svn: 160475
* ignore 'invoke @llvm.donothing', but still keep the edge to the continuation BBNuno Lopes2012-07-181-1/+1
| | | | llvm-svn: 160411
* Back out r160101 and instead implement a dag combine to recover from ↵Evan Cheng2012-07-171-0/+28
| | | | | | instcombine transformation. llvm-svn: 160387
* Remove unused variable.Benjamin Kramer2012-07-171-1/+0
| | | | llvm-svn: 160372
* Fix a crash in the legalization of large vectors.Nadav Rotem2012-07-171-6/+3
| | | | | | | When truncating a result of a vector that is split we need to use the result of the split vector, and not re-split the dead node. llvm-svn: 160357
* Implement r160312 as target indepedenet dag combine.Evan Cheng2012-07-171-0/+27
| | | | llvm-svn: 160354
* Make sure constant bitwidth is <= 64 bit before calling getSExtValue().Evan Cheng2012-07-171-1/+2
| | | | llvm-svn: 160350
* This is another case where instcombine demanded bits optimization createdEvan Cheng2012-07-171-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 llvm-svn: 160346
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